a
Multiformat Progressive Scan/HDTV
Encoder with Three 11-Bit DACs
and 10-Bit Data Input
ADV7195
FUNCTIONAL BLOCK DIAGRAM
SHARPNESS
FILTER CONTROL
AND
ADAPTIVE
FILTER CONTROL
FEATURES
INPUT FORMATS
YCrCb in 2 10-Bit (4:2:2) or 3 10-Bit (4:4:4) Format-
Compliant to SMPTE-293M (525p), ITU-R.BT1358
(625p), SMPTE274M (1080i), SMPTE296M (720p)
and Any Other High-Definition Standard Using
Async Timing Mode
RGB in 3 10 Bit (4:4:4) Format
OUTPUT FORMATS
YPrPb Progressive Scan (EIA-770.1, EIA-770.2)
YPrPb HDTV (EIA-770.3)
RGB Levels Compliant to RS-170 and RS-343A
11-Bit + Sync (DAC A)
11-Bit DACs (DAC B, DAC C)
PROGRAMMABLE FEATURES
Internal Test Pattern Generator with Color Control
Y/C Delay ( )
Gamma Correction
Individual DAC On/Off Control
54 MHz Output (2 Oversampling)
Sharpness Filter with Programmable Gain/Attenuation
Programmable Adaptive Filter Control
Undershoot Limiter
VBI Open Control
I
2
C
®
Filter
CGMS-A (525p)
2-Wire Serial MPU Interface
Single Supply 3.3 V Operation
52-MQFP Package
APPLICATIONS
Progressive Scan/HDTV Display Devices
MPEG at 81 MHz
Progressive Scan/HDTV Projection Systems
Digital Video Systems
High Resolution Color Graphics
Image Processing/Instrumentation
Digital Radio Modulation/Video Signal Reconstruction
ADV7195
CGMS
MACROVISION
11-BIT+
SYNC
DAC
Y0–Y9
TEST PATTERN
GENERATOR
AND
DELAY
AND
GAMMA
CORRECTION
CHROMA
4:2:2
TO
4:4:4
(SSAF)
CHROMA
4:2:2
TO
4:4:4
(SSAF)
LUMA
SSAF
DAC A (Y)
Cr0–Cr9
11-BIT
DAC
2 INTER-
POLATION
11-BIT
DAC
DAC B
Cb0–Cb9
DAC C
CLKIN
HORIZONTAL
SYNC
VERTICAL
SYNC
BLANKING
RESET
TIMING
GENERATOR
I C MPU
PORT
2
SYNC
GENERATOR
DAC CONTROL
BLOCK
V
REF
RESET
COMP
The ADV7195 has three separate 10-bit-wide input ports that
accept data in 4:4:4 10-bit YCrCb or RGB or 4:2:2 10-bit YCrCb.
This data is accepted in progressive scan format at 27 MHz or
HDTV format at 74.25 MHz or 74.1758 MHz. For any other
high-definition standard but SMPTE293M, ITU-R BT.1358,
SMPTE274M or SMPTE296M the Async Timing Mode can
be used to input data to the ADV7195. For all standards, exter-
nal horizontal, vertical, and blanking signals or EAV/SAV codes
control the insertion of appropriate synchronization signals into
the digital data stream and therefore the output signals.
The ADV7195 outputs analog YPrPb progressive scan format
complying to EIA-770.1, EIA-770.2; YPrPb HDTV complying
to EIA-770.3; RGB complying to RS-170/RS-343A.
The ADV7195 requires a single 3.3 V power supply, an
optional external 1.235 V reference and a 27 MHz clock in
Progressive Scan Mode or a 74.25 MHz (or 74.1758 MHz)
clock in HDTV mode.
In Progressive Scan Mode, a sharpness filter with programmable
gain allows high-frequency enhancement on the luminance signal.
Programmable Adaptive Filter Control, which may be used,
allows removal of ringing on the incoming Y data. The ADV7195
supports CGMS-A data control generation.
The ADV7195 is packaged in a 52-lead MQFP package.
GENERAL DESCRIPTION
The ADV7195 is a triple high-speed, digital-to-analog encoder
on a single monolithic chip. It consists of three high-speed video
D/A converters with TTL-compatible inputs.
I
2
C is a registered trademark of Philips Corporation.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
ADV7195
TABLE OF CONTENTS
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1
FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1
3.3 V SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 V DYNAMIC–SPECIFICATIONS . . . . . . . . . . . . . . . . . . 4
3.3 V TIMING–SPECIFICATIONS . . . . . . . . . . . . . . . . . . 5
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 8
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 9
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . 10
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Undershoot Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
I
2
C Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Internal Test Pattern Generator . . . . . . . . . . . . . . . . . . . . 10
Y/CrCb Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Gamma Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
54 MHz Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PROGRAMMABLE SHARPNESS FILTER . . . . . . . . . . . 10
PROGRAMMABLE ADAPTIVE FILTER CONTROL . . 11
INPUT/OUTPUT CONFIGURATION . . . . . . . . . . . . . . 11
MPU PORT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . 11
REGISTER ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
REGISTER PROGRAMMING . . . . . . . . . . . . . . . . . . . . . 13
Subaddress Register (SR7–SR0) . . . . . . . . . . . . . . . . . . . 13
Register Select (SR6–SR0) . . . . . . . . . . . . . . . . . . . . . . . . 13
PROGRESSIVE SCAN MODE . . . . . . . . . . . . . . . . . .
14
MODE REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
MR0 (MR07–MR00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
MR0 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output Standard Selection (MR00–MR01) . . . . . . . . . . . 14
Input Control Signals (MR02–MR03) . . . . . . . . . . . . . . . 14
Input Standard (MR04) . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Reserved (MR05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DV Polarity (MR06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Reserved (MR07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
MODE REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
MR1 (MR17–MR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
MR1 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 16
Pixel Data Enable (MR10) . . . . . . . . . . . . . . . . . . . . . . . . 16
Input Format (MR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Test Pattern Enable (MR12) . . . . . . . . . . . . . . . . . . . . . . 16
Test Pattern Hatch/Frame (MR13) . . . . . . . . . . . . . . . . . 16
VBI Open (MR14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Undershoot Limiter (MR15–MR16) . . . . . . . . . . . . . . . . 16
Sharpness Filter (MR17) . . . . . . . . . . . . . . . . . . . . . . . . . 16
MODE REGISTER 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
MR1 (MR27–MR20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
MR2 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 17
Y Delay (MR20–MR22) . . . . . . . . . . . . . . . . . . . . . . . . . 17
Color Delay (MR23–MR25) . . . . . . . . . . . . . . . . . . . . . . 17
CGMS Enable (MR26) . . . . . . . . . . . . . . . . . . . . . . . . . . 17
CGMS CRC (MR27) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
MODE REGISTER 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
MR3 (MR37–MR30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
MR3 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 18
HDTV Enable (MR30) . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Reserved (MR31–MR32) . . . . . . . . . . . . . . . . . . . . . . . . . 18
DAC A Control (MR33) . . . . . . . . . . . . . . . . . . . . . . . . . 18
DAC B Control (MR34) . . . . . . . . . . . . . . . . . . . . . . . . . 18
DAC C Control (MR35) . . . . . . . . . . . . . . . . . . . . . . . . . 18
Interpolation (MR36) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Reserved (MR37) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
MODE REGISTER 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
MR4 (MR47–MR40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
MR4 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 18
Timing Reset (MR40) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
MODE REGISTER 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
MR5 (MR57–MR50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
MR5 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 18
Reserved (MR50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
RGB Mode (MR51) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Sync on PrPb (MR52) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Color Output Swap (MR53) . . . . . . . . . . . . . . . . . . . . . . 19
Gamma Curve (MR54) . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Gamma Correction (MR55) . . . . . . . . . . . . . . . . . . . . . . 19
Adaptive Mode Control (MR56) . . . . . . . . . . . . . . . . . . . 19
Adaptive Filter Control (MR57) . . . . . . . . . . . . . . . . . . . 19
COLOR Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
CY (CY7–CY0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
COLOR CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
CCR (CCR7–CCR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
COLOR CB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
CCB (CCB7–CCB0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
MODE REGISTER 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
MR6 (MR67–MR60) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
MR6 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 20
MR67–MR60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
CGMS DATA REGISTERS 2–0 . . . . . . . . . . . . . . . . . . . . 20
CGMS2 (CGMS27–CGMS20) . . . . . . . . . . . . . . . . . . . . 20
CGMS1 (CGMS17–CGMS10) . . . . . . . . . . . . . . . . . . . . 20
CGMS0 (CGMS07–CGMS00) . . . . . . . . . . . . . . . . . . . . 20
FILTER GAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
FG (FG7–FG0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
FG BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Filter Gain A (FG3–FG0) . . . . . . . . . . . . . . . . . . . . . . . . 21
Filter Gain B (FG4–FG7) . . . . . . . . . . . . . . . . . . . . . . . . 21
GAMMA CORRECTION REGISTERS 0–13
(GAMMA CORRECTION 0–13) . . . . . . . . . . . . . . . . . . 21
SHARPNESS FILTER CONTROL AND
ADAPTIVE FILTER CONTROL . . . . . . . . . . . . . . . . . 22
SHARPNESS FILTER MODE . . . . . . . . . . . . . . . . . . . . . 22
ADAPTIVE FILTER MODE . . . . . . . . . . . . . . . . . . . . . . . 22
ADAPTIVE FILTER GAIN 1 . . . . . . . . . . . . . . . . . . . . . . 23
AFG1 (AFG1)7–0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
ADAPTIVE FILTER GAIN 2 . . . . . . . . . . . . . . . . . . . . . . 23
AFG2 (AFG2)7–0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
ADAPTIVE FILTER GAIN 3 . . . . . . . . . . . . . . . . . . . . . . 23
AFG3 (AFG3)7–0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
–2–
REV. A
ADV7195
ADAPTIVE FILTER THRESHOLD A . . . . . . . . . . . . . . . 23
AFTA AFTA7–0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
ADAPTIVE FILTER THRESHOLD B . . . . . . . . . . . . . . . 23
AFTB AFTB7–0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
ADAPTIVE FILTER THRESHOLD C . . . . . . . . . . . . . . . 23
AFTC AFTC7–0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SHARPNESS FILTER AND ADAPTIVE FILTER
APPLICATIONS EXAMPLES . . . . . . . . . . . . . . . . . . . . 24
Sharpness Filter Application . . . . . . . . . . . . . . . . . . . . . . 24
Adaptive Filter Control Application . . . . . . . . . . . . . . . . . 25
HDTV MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
MODE REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
MR0 (MR07–MR00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
MR0 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 26
Output Standard Selection (MR00-MR01) . . . . . . . . . . . 26
Input Control Signals (MR02–MR03) . . . . . . . . . . . . . . . 26
Reserved (MR04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Input Standard (MR05) . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DV Polarity (MR06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Reserved (MR07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
MODE REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
MR1 (MR17–MR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
MR1 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 27
Pixel Data Enable (MR10) . . . . . . . . . . . . . . . . . . . . . . . . 27
Input Format (MR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Test Pattern Enable (MR12) . . . . . . . . . . . . . . . . . . . . . . 27
Test Pattern Hatch/Frame (MR13) . . . . . . . . . . . . . . . . . 27
VBI Open (MR14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Reserved (MR15–MR17) . . . . . . . . . . . . . . . . . . . . . . . . . 27
MODE REGISTER 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
MR1 (MR27–MR20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
MR2 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 28
Y Delay (MR20–MR22) . . . . . . . . . . . . . . . . . . . . . . . . . 28
Color Delay (MR23–MR25) . . . . . . . . . . . . . . . . . . . . . . 28
Reserved (MR26–MR27) . . . . . . . . . . . . . . . . . . . . . . . . . 28
MODE REGISTER 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
MR3 (MR37–MR30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
MR3 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 28
HDTV Enable (MR30) . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Reserved (MR31–MR32) . . . . . . . . . . . . . . . . . . . . . . . . . 28
DAC A Control (MR33) . . . . . . . . . . . . . . . . . . . . . . . . . 28
DAC B Control (MR34) . . . . . . . . . . . . . . . . . . . . . . . . . 28
DAC C Control (MR35) . . . . . . . . . . . . . . . . . . . . . . . . . 28
Reserved (MR36–MR37) . . . . . . . . . . . . . . . . . . . . . . . . . 28
MODE REGISTER 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
MR4 (MR47–MR40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
MR4 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 29
Timing Reset (MR40) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Reserved (MR41–MR47) . . . . . . . . . . . . . . . . . . . . . . . . . 29
MODE REGISTER 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
MR5 (MR57–MR50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
MR5 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 29
Reserved (MR50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
RGB Mode (MR51) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Sync on PrPb (MR52) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Color Output Swap (MR53) . . . . . . . . . . . . . . . . . . . . . . 29
Reserved (MR54–MR57) . . . . . . . . . . . . . . . . . . . . . . . . . 29
DAC TERMINATION AND LAYOUT
CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PC BOARD LAYOUT CONSIDERATIONS . . . . . . . . . . 30
Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Digital Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . . 31
Analog Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . 31
Video Output Buffer and Optional Output Filter . . . . . . . 31
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 36
REV. A
–3–
ADV7195–SPECIFICATIONS
3.3 V SPECIFICATIONS
Parameter
STATIC PERFORMANCE
Resolution (Each DAC)
Integral Nonlinearity
1
Differential Nonlinearity
1
DIGITAL OUTPUTS
Output Low Voltage, V
OL
Output High Voltage, V
OH
Three-State Leakage Current
Three-State Output Capacitance
DIGITAL AND CONTROL INPUTS
Input High Voltage, V
IH
Input Low Voltage, V
IL
Input Current, I
IN
Input Capacitance, C
IN
ANALOG OUTPUTS
Full-Scale Output Current
Output Current Range
DAC-to-DAC Matching
Output Compliance Range, V
OC
Output Impedance, R
OUT
Output Capacitance, C
OUT
VOLTAGE REFERENCE (External)
Reference Range, V
REF
POWER REQUIREMENTS
I
DD2
(V
AA
= 3.15 V to 3.45 V, V
REF
= 1.235 V, R
SET
= 2470
to 70 C] unless otherwise noted, TJ
MAX
= 110 C.)
Min
Typ
11
1.5
0.9
Max
, R
LOAD
= 300
Unit
Bits
LSB
LSB
V
V
µA
pF
V
V
µA
pF
mA
mA
mA
mA
%
V
kΩ
pF
V
mA
mA
mA
mA
.
All specifications T
MIN
to T
MAX
[0 C
Test Conditions
2.0
0.4
2.4
10
4
2
0.8
0
4
3.92
2.54
3.92
2.39
0
4.25
2.83
4.25
2.66
1.4
1.4
100
7
1.235
25
51
40
11
0.65
I
SINK
= 3.2 mA
I
SOURCE
= 400
µA
V
IN
= 0.4 V
V
IN
= 0.0 V or V
DD
4.56
3.11
4.56
2.93
DAC A
DAC B, DAC C
DAC A
DAC B, DAC C
1.112
1.359
35
60
I
AA3, 4
I
PLL
Power Supply Rejection Ratio
15
6.0
12
mA
1× Interpolation
2× Interpolation
HDTV Mode
(With f
CLK
= 7425 MHz)
1× Interpolation,
2× Interpolation, and
HDTV Mode
1× Interpolation,
2× Interpolation, and
HDTV Mode
0.01
%/%
NOTES
1
Guaranteed by characterization.
2
I
DD
or the circuit current is the continuous current required to drive the digital core without I
PLL
.
3
I
AA
is the total current required to supply all DACs, including the V
REF
circuitry.
4
All DACs On.
Specifications subject to change without notice.
3 V DYNAMIC–SPECIFICATIONS
Parameter
Luma Bandwidth
Chroma Bandwidth
Signal-to-Noise Ratio
Chroma/Luma Delay Inequality
Specifications subject to change without notice.
(V
AA
= 3.15 V to 3.45 V, V
REF
= 1.235 V, R
SET
= 2470
T
MIN
to T
MAX
[0 C to 70 C] unless otherwise noted.)
Typ
13.5
6.75
64
0
Max
, R
LOAD
= 300
Unit
. All specifications
Min
MHz
MHz
dB Luma Ramp Unweighted
ns
–4–
REV. A
ADV7195
3.3 V TIMING–SPECIFICATIONS
P
arameter
MPU PORT
1
SCLOCK Frequency
SCLOCK High Pulsewidth, t
1
SCLOCK Low Pulsewidth, t
2
Hold Time (Start Condition), t
3
Setup Time (Start Condition), t
4
Data Setup Time, t
5
SDATA, SCLOCK Rise Time, t
6
SDATA, SCLOCK Fall Time, t
7
Setup Time (Stop Condition), t
8
RESET Low Time
ANALOG OUTPUTS
Analog Output Delay, t
62
Analog Output Skew
CLOCK CONTROL AND PIXEL PORT
3
f
CLK
Min
0
0.6
1.3
0.6
0.6
100
(V
AA
= 3.15 V to 3.45 V, V
REF
= 1.235 V, R
SET
= 2470
T
MIN
to T
MAX
[0 C to 70 C] unless otherwise noted.)
Typ
Max
400
Unit
kHz
µs
µs
µs
µs
ns
ns
ns
µs
ns
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
Clock Cycles
Clock Cycles
Conditions
, R
LOAD
= 300
. All specifications
After this Period the 1st Clock Is Generated
Relevant for Repeated Start Condition
300
300
0.6
100
10
0.5
27
74.25
81
21.5
22.0
3.4
3.2
3.4
3.2
Progressive Scan Mode
HDTV Mode
ASYNC Timing Mode and 1× Interpolation
Clock High Time, t
9
Clock Low Time, t
10
Data Setup Time, t
11
Data Hold Time, t
12
Control Setup Time, t
11
Control Hold Time, t
12
Pipeline Delay
Pipeline Delay
5.0
5.0
2.0
4.5
7.0
4.0
16
29
For 4:4:4 Pixel Input Format at 1× Oversampling
For 4:4:4 or 4:2:2 Pixel Input Format at
2× Oversampling
NOTES
1
Guaranteed by characterization.
2
Output delay measured from 50% point of rising edge of CLOCK to the 50% point of DAC output full-scale transition.
3
Data: Cb/Cr(9–0), Cr(9–0), Y(9–0); Control:
HSYNC/SYNC, VSYNC/TSYNC,
DV.
Specifications subject to change without notice.
REV. A
–5–
Power technology
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