ADV7400A
ELECTRICAL CHARACTERISTICS
A
VDD
= 3.15 V to 3.45 V, D
VDD
= 1.65 V to 2.0 V, D
VDDIO
= 3.0 V to 3.6 V, P
VDD
= 1.65 V to 2.0 V, nominal input range = 1.6 V, operating
temperature range, unless otherwise noted.
Table 1. Electrical Characteristics
1
,
2
Parameter
STATIC PERFORMANCE
3
Resolution (each ADC)
Integral Nonlinearity
Integral Nonlinearity
Integral Nonlinearity
Integral Nonlinearity
Differential Nonlinearity
Differential Nonlinearity
Differential Nonlinearity
Differential Nonlinearity
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
XTAL High Voltage
XTAL Low Voltage
Input High Voltage
Input Low Voltage
Input Current
Input Capacitance
6
DIGITAL OUTPUTS
Output High Voltage
Output Low Voltage
High Impedance Leakage Current
Output Capacitance
6
POWER REQUIREMENTS
6
Digital Core Power Supply
Digital I/O Power Supply
PLL Power Supply
Analog Power Supply
Digital Core Supply Current
Digital I/O Supply Current
PLL Supply Current
Analog Supply Current
Power-Down Current
Green Mode Power-Down
Power-Up Time
1
2
Symbol
N
INL
INL
INL
INL
DNL
DNL
DNL
DNL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
I
IN
C
IN
V
OH
V
OL
I
LEAK
C
OUT
D
VDD
D
VDDIO
P
VDD
A
VDD
I
DVDD
I
DVDDIO
I
PVDD
I
AVDD
I
PWRDN
I
PWRDNG
T
PWRUP
Test Conditions
Min
Typ
Max
10
±2.5
Unit
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
V
V
V
V
V
V
µA
µA
pF
V
V
µA
µA
pF
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
ms
BSL at 27 MHz (at a 10-bit level)
BSL at 54 MHz (at a 10-bit level)
BSL at 74 MHz (at a 10-bit level)
BSL at 110 MHz (at an 8-bit level)
4
At 27 MHz (at a 10-bit level)
At 54 MHz (at a 10-bit level)
At 74 MHz (at a 10-bit level)
At 110 MHz (at an 8-bit level)
4
2
±0.6
−0.6/+0.7
−1.2/+1.5
−0.9/+1.6
−0.2/+0.25
−0.2/+0.25
±0.8
−0.2/+1.5
−0.3/+0.7
0.8
Pin 38
Pin 38
HS_IN, VS_IN low trigger mode
HS_IN, VS_IN low trigger mode
Pins listed in Note 5
All other input pins
1.2
0.4
0.7
−60
−10
0.4
+60
+10
10
I
SOURCE
= 0.4 mA
I
SINK
= 3.2 mA
Pins listed in Note 7
All other output pins
2.4
0.4
60
10
20
1.65
3.0
1.65
3.15
1.8
3.3
1.8
3.3
82
62
2
17
10.5
6
85
218
1.5
12.5
20
2
3.6
2
3.45
CVBS input sampling at 54 MHz
Graphics RGB sampling at 110 MHz
CVBS input sampling at 54 MHz
Graphics RGB sampling at 110 MHz
54 MHz
110 MHz
CVBS input sampling at 54 MHz
Graphics RGB sampling at 110 MHz
Sync bypass function
4
4
4
The min/max specifications are guaranteed over this range.
Temperature range T
MIN
to T
MAX
:
−40°C
to +85°C.
3
All ADC linearity tests performed at input range of full scale are
−12.5%,
and at zero scale they are +12.5%.
4
Specifications for the ADV7400AKSTZ-110 and the ADV7400ABSTZ-110 only.
5
Pins: 1, 2, 3, 13, 14, 16, 19, 24, 29, 30, 31, 32, 33, 34, 35, 45, 79, 83, 84, 87, 88, 95, 96, 97, 100.
6
Guaranteed by characterization.
7
Pins: 45, 34, 33, 32, 31, 30, 29, 24, 14, 13 (P20 to P29).
Rev. A | Page 3 of 16
ADV7400A
VIDEO SPECIFICATIONS
A
VDD
= 3.15 V to 3.45 V, D
VDD
= 1.65 V to 2.0 V, D
VDDIO
= 3.0 V to 3.6 V, P
VDD
= 1.65 V to 2.0 V, operating temperature range, unless
otherwise noted.
Table 2. Video Specifications
1, 2, 3
Parameter
NONLINEAR SPECIFICATIONS
Differential Phase
Differential Gain
Luma Nonlinearity
NOISE SPECIFICATIONS
SNR Unweighted
SNR Unweighted
Analog Front End Crosstalk
LOCK TIME SPECIFICATIONS
Horizontal Lock Range
Vertical Lock Range
F
SC
Subcarrier Lock Range
Color Lock in Time
Sync Depth Range
Color Burst Range
Vertical Lock Time
Horizontal Lock Time
CHROMA SPECIFICATIONS
Hue Accuracy
Color Saturation Accuracy
Color AGC Range
Chroma Amplitude Error
Chroma Phase Error
Chroma Luma Intermodulation
LUMA SPECIFICATIONS
Luma Brightness Accuracy
Luma Contrast Accuracy
1
2
Symbol
DP
DG
LNL
Test Conditions
CVBS I/P, modulated 5 step
CVBS I/P, modulated 5 step
CVBS I/P, 5 step
Luma ramp
Luma flat field
Min
Typ
0.5
0.5
0.5
Max
0.7
0.7
0.7
Unit
degree
%
%
dB
dB
dB
54
58
56
60
60
+5
70
±1.3
60
−5
40
20
5
2
100
HUE
CL_AC
5
0.5
0.4
0.2
CVBS, 1 V input
CVBS, 1 V input
1
1
1
1
200
200
%
Hz
kHz
line
%
%
field
line
degree
%
%
%
degree
%
%
%
400
The min/max specifications are guaranteed over this range.
Temperature range T
MIN
to T
MAX
:
−40°C
to +85°C.
3
Guaranteed by characterization.
Rev. A | Page 4 of 16
ADV7400A
TIMING CHARACTERISTICS
A
VDD
= 3.15 V to 3.45 V, D
VDD
= 1.65 V to 2.0 V, D
VDDIO
= 3.0 V to 3.6 V, P
VDD
= 1.65 V to 2.0 V, operating temperature range, unless
otherwise noted.
Table 3. Timing Characteristics
1, 2, 3
Parameter
SYSTEM CLOCK AND CRYSTAL
Crystal Nominal Frequency
Crystal Frequency Stability
Horizontal Sync Input Frequency
LLC1 Frequency Range
4
I
2
C® PORT
SCLK Frequency
SCLK Min Pulse Width High
SCLK Min Pulse Width Low
Hold Time (Start Condition)
Setup Time (Start Condition)
SDA Setup Time
SCLK and SDA Rise Time
SCLK and SDA Fall Time
Setup Time for Stop Condition
RESET FEATURE
Reset Pulse Width
CLOCK OUTPUTS
LLC1 Mark Space Ratio
DATA and CONTROL OUTPUTS
Data Output Transition Time (SDP)
Data Output Transition Time (SDP)
Data Output Transition Time (CP)
Data Output Transition Time (CP)
Data Output Transition Time DDR (CP)
5
Data Output Transition Time DDR (CP)
5
Data Output Transition Time DDR (CP)
5
Data Output Transition Time DDR (CP)
5
DATA and CONTROL INPUTS
Input Setup Time
Input Hold Time
1
2
Symbol Test Conditions
Min
Typ
27.0
Max
Unit
MHz
ppm
kHz
MHz
kHz
µs
µs
µs
µs
ns
ns
ns
µs
ms
14.8
12.825
±50
110
110
400
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
0.6
1.3
0.6
0.6
100
300
300
0.6
5
t
9
:t
10
45:55
55:45 % duty
cycle
3.4
2.4
1.1
2.2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
11
t
12
t
13
t
14
t
15
t
16
t
17
t
18
t
19
t
20
Negative clock edge to start of valid data
End of valid data to negative clock edge
End of valid data to negative clock edge
Negative clock edge to start of valid edge
Positive clock edge to end of valid data
Start of valid data to positive clock edge
Negative clock edge to end of valid data
Start of valid data to negative clock edge
HS_IN, VS_IN
DE_IN, data inputs
HS_IN, VS_IN
DE_IN, data inputs
−2.7 + T
LLC1
/4
−1.3 + T
LLC1
/4
−2.1 + T
LLC1
/4
−0.9 + T
LLC1
/4
9
2.2
7
1
The min/max specifications are guaranteed over this range.
Temperature range T
MIN
to T
MAX
:
−40°C
to +85°C.
3
Guaranteed by characterization.
4
Maximum LLC1 frequency is 80 MHz for the ADV7400AKSTZ-80.
5
DDR timing specifications depend on LLC1 output pixel clock; T
LCC1
/4 = 9.25 ns at LLC1 = 27 MHz.
Rev. A | Page 5 of 16
FPGA/CPLD
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