Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
16-Bit I/O Expander IC
PT8300
DESCRIPTION
PT8300 is an I/O expander utilizing CMOS technology providing 16 bits serial input-parallel output and
8 bits parallel input-serial output shift register function. 8 input pins or 16 output pins can be configured
to a cascading or parallel structure. Reading of serial data during the parallel to serial data conversion
is enabled by the built-in independent registers for serial input to parallel output and parallel input to
serial output. Housed in 28 pins, SOP Package, PT8300 provides 8 input or 16 output pins which can
be configured into a cascading structure. Pin assignments and application circuits are optimized for
easy PCB layout and cost saving benefits.
FEATURES
•
CMOS technology
•
Low power consumption:
- Wide operating supply voltage range: V
DD
=3 to 5.5V
- Wide operating temperature range: Ta=-20 to +75℃
•
Reading of the serial data during parallel to serial data conversion
•
8 output pins or 8 input/output pins provided
•
Schmitt triggered inputs (DI1,DI2,CLK,LATCH, /RESET,PULLUP)
•
Parallel data inputs provided (P8 to P15)
•
Open drain with selectable pull up resistance ports provided (P8 to P15)
•
Normal output ports provided (P0 to P7)
•
Port extension is supported
APPLICATIONS
•
MCU peripheral device
•
Serial bus system data communication
PT8300 V1.8
-1-
February, 2006
PT8300 V1.8
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10 P11
P12
P13 P4
P15
16-Bit I/O Expander IC
PULLUP
27
BLOCK DIAGRAM
VDD
28
VSS
1
-2-
LATCH
RESET
I0
I7
Latch 16-Bit
I8
O0
O7
O8
CLK
DI
RESET
Q0
Shift Register 1: 16-Bit Shift Register Serial to Parallel
CLK
DI
D0
Shift Register 2: 16-Bit Shift Register Parallel to Serial
LATCH
4
O15
I15
CLK
3
DI1
26
Q15
DO
/RESET
2
14
D15
DO
CLKO
DI2
16
LATCHO
13
DO2
25
DO1
15
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
February, 2006
PT8300
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
16-Bit I/O Expander IC
PT8300
PIN CONFIGURATION
VSS
/RESET
CLK
LATCH
P15
P14
P13
P12
P11
P10
P9
P8
LATCHO
CLKO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
PULLUP
DI1
DO2
P0
P1
P2
P3
P4
P5
P6
P7
DI2
DO1
PT8300
PIN DESCRIPTION
Pin Name
VSS
/RESET
CLK
LATCH
P15 ~ P8
LATCHO
CLKO
DO1, DO2
DI1, DI2
P7 ~ P0
PULLUP
VDD
I/O
-
I
I
I
I/O
O
O
O
I
O
I
-
Description
Ground
Reset pin (Active: Low)
Clock input pin
Latch input pin
Parallel data input/output pins
Latch output pin
Clock output pin
Serial data output pins
Serial data input pins
Parallel data output pins
P8 to P15 control pin for internal resistor
When P8 to P15 are in the output state, the PULLUP pin must be
connected to V
DD
.
When P8 to P15 are in the input state, the PULLUP pin must be
connected to VSS.
Pin No.
1
2
3
4
5 ~ 12
13
14
15, 25
26, 16
17 ~ 24
27
28
PT8300 V1.8
-3-
February, 2006
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
16-Bit I/O Expander IC
PT8300
FUNCTION DESCRIPTION
PT8300 is an I/O Expander IC which independently generates a 16-bit serial input-to-parallel output
shift register and a parallel input-to-serial output shift register for the purpose of reading the serial input
data that is generated during the parallel to serial data output conversion.
When the /RESET Pin is connected to VSS, the outputs of pins -- P0 to P7 are 0. If the PULLUP pin is
connected to VSS or open, the outputs of pins -- P8 to P15 are floating. If the PULLUP pin is connected
to VDD, the P8 to P15 pins are 1.
NO USED PINS
If any of the Input, Output or I/O (P8 to P15) pins are not used, then the following conditions listed in the
table must be carefully followed.
When an output pin is not used, it must keep OPEN. The unused input pin must only be set to either
HIGH or LOW. It should be noted that when an input pin is not used, it cannot be OPEN.
When the I/O Pins -- P8 to P15 -- are not used, certain conditions must be followed. If any of these pins,
P8 to P15 are connected to VSS, the PULLUP Pin must also be connected to VSS. If any of these pins
-- P8 to P15 -- are connected to VDD, then the Internal Shift Register 1 (Q8 to Q15) must be set to 1. If
these pins -- P8 to P15 -- are not connected to either VSS or VDD, then any one of the following
conditions must be followed:
1) PULLUP pin must be connected to VDD and the Shift Register 1 (Q8 to Q15) must be set to 1, or
2) PULLUP pin must be connected to VSS and the Shift Register 1 (Q8 to Q15) must be set to 0.
It must be noted that when P8 to P15 are not in used, they must be set to HIGH or LOW.
Type of Pin Not Used
Output pin
Input pin
Condition
The unused output pin must be kept OPEN or not connected
The unused input pin must either be set to HIGH or LOW.
It cannot be kept OPEN.
Connected to VSS
PULLUP pin must be connected to VSS
Connected to VDD
Shift register 1 (Q1 to Q15) is set to 1
Any one of the conditions must be followed:
1. PULLUP pin is connected to VDD and shift
register 1 (Q1 to Q15) is set to 1.
No Connection
2. PULLUP pin is connected to VSS, and shift
register 1 (Q8 to Q15) is set to 0.
3. When P8 to P15 are not in used, they must
either be set to HIGH or LOW.
I/O pin (P8 to P15)
PT8300 V1.8
-4-
February, 2006
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
16-Bit I/O Expander IC
PT8300
OPERATION
1. P0 to P15 are undefined when power is turned ON, but if /RESET is set to LOW, P0 to P7 are in
LOW state. If PULLUP pin is connected to VSS, P8 to P15 are floating. If PULLUP pin is
connected to VDD, P8 to P15 are in HIGH State.
2. The status of P0 to P15 is loaded to the Shift register 1 at the falling edge of LATCH/LATCHO.
3. At the falling edge of the CLK, the 16-bit serial output of the data loaded to the Shift register 1 (Shift
register 2) is sequentially performed from DO1(DO2).
4. At the rising edge of CLK, 16-bit serial data is written into the Shift register 1 (Shift register 2)
from DI1(DI2).
5. At the rising edge of the LATCH/LATCHO, the data written is outputted in a parallel manner to the
P0 to P15.
6. Shift Register 1 loads the data that is to be applied externally and the data with the latched content.
to the parallel output latch.
7. When the LATCH/LATCHO is activated after the arrival of CLK’s 16th bit, the parallel output
latch sends out P0 to P15 by storing the data that has been written into the Shift register 2. The
Shift Registers 1 and 2 continue the shift operation until the CLK’s 16th bit and the DO1 (DO2)
output serial data arrive.
8. Serial data is used to control the switching mode operation (input
↔
output) of P8 to P15. When
P8 to P15 operate as Output Pins, the PULLUP must be set to HIGH.
OPERATION TIMING DIAGRAM
/RESET
LATCH/LATCHO
CLK/CLKO
DI1/DI2
DO1/DO2
P0
P1
P15
1
2
3
4
5
16
DI0
DI1
DI2
DI3
DI1 5
DO 0
DO 1
DO 2
DO 3
DO 1 5
DI
0-1
DI0
DI
1-1
DI1
DI
15-1
DI1 5
PT8300 V1.8
-5-
February, 2006
京公网安备 11010802033920号
EEWORLD
