Preliminary
PT9120
GPS Receiver RF Front End IC
DESCRIPTION
The PT9120 is a single chip Global Positioning
System (GPS) receiver front-end IC requiring few
external components and offering extremely low
power consumption. The PT9120 employs a
super-heterodyne receiver topology which
down-converts the 1575.42MHz L1-band GPS
signal to a 1st IF. The 1st IF is then filtered by an
off-chip L-C filter and subsequently sub-sampled
by the 2-bit A/D converter to provide both sign and
magnitude quantized CMOS level outputs to base
band inputs.
FEATURES
•
•
•
•
•
•
GPS L1-band (C/A code) receiver
Integrated LNA and antenna detector
Fully-monolithic VCO
Support for several reference frequencies
2-bit ADC output (sign and magnitude)
Extremely low current consumption (7mA at
AVDD=DVDD=2.5V)
•
Multiple power-down modes
•
Available in 28 pins or 24 pins, QFN package
APPLICATION
•
GPS systems
BLOCK DIAGRAM
Tel: 886-66296288
‧
Fax: 886-29174598
‧
http://www.princeton.com.tw
‧
2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan
PT9120
PIN DESCRIPTION
Pin Name
SGN
MAG
AOK
CP
DVSS
DVDD
XEN
XO
XI
VB
PLL
AON
LNI
ISNS
PVDD
LNO
AVDD
AVSS
RFIN
VBG
IF1P
IF1N
IF2P
IF2N
MODE
AGC
P1
P0
I/O
O
O
O
I/O
G
P
I
O
I
O
O
O
I
I
O
O
P
G
I
O
O
O
I
I
I
I/O
I
I
Description
Quantized 2nd IF “sign” bit
Quantized 2nd IF “magnitude” bit
Active antenna status output (AOK = HIGH = active antenna OK;
AOK=LOW=active antenna either open or shorted)
Reference clock input/output
Ground (digital circuitry)
Supply voltage (digital circuitry)
Crystal oscillator enable pin
(XEN=HIGH=enabled; XEN=LOW=disabled)
Crystal oscillator output
Crystal oscillator input
Regulator (1.9V) output
Charge pump output
Antenna switch-controlled supply voltage to active antenna
LNA input
Antenna detector current sense input
Supply voltage (active antenna)
LNA output
Supply voltage (analog circuitry)
Ground (analog circuitry)
Mixer input
Band gap reference (1.23V) output
Differential mixer IF output/differential first-stage IF amplifier input
Differential first-stage IF amplifier output/differential IF AGC input
Reference frequency mode select input
AGC capacitor connection. Sets the AGC time constant.
Power-down control pins (see PT9120 operating modes)
Pin No.
28-pin
24-pin
1
1
2
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
-
3
4
5
6
7
-
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
-
23
24
-
PRE1.3
4
PT9120
FUNCTION DESCRIPTION
The PT9120 low power GPS receiver IC employs a double-conversion, super-heterodyne receiver topology to achieve
excellent performance. A complete GPS L1-band receiver front-end may be constructed using the PT9120 IC together
with an active antenna, RF and IF filters, and a reference crystal.
The PT9120 consists of an RF LNA; an RF mixer; complete frequency synthesizer including a VCO, phase/frequency
detector (PFD), charge pump, input and reference dividers, and a reference crystal oscillator; IF AGC amplifier; and a
2-bit A/D converter with CMOS-level outputs. The PT9120 includes an on-chip voltage regulator and an integrated
antenna detector and switch capable of supplying power to an active antenna as well as providing current limiting
protection when an antenna open or short has been detected. The on-chip voltage regulator provides a stable 1.9V
output at the VB pin. In addition, the PT9120 implements four distinct operating modes including two low power modes
and one complete power-down mode.
The application circuit includes the PT9120 IC and provides an option for either a patch antenna or active antenna, a
single connector to a power supply, power-down control inputs, and digital data outputs. Among the various external
parts are an external LNA, filter and oscillator components (TCXO), de-coupling resistors and capacitors for the analog
and digital power supplies, and the SAW filter between the discrete LNA output and the PT9120 RF input.
ANTENNA DETECTOR/SWITCH
The PT9120 integrates an antenna detector and switch to supply power to and control an optional active antenna. The
supply voltage for an active antenna is applied to the PT9120’s PVDD pin. The actual voltage supply connection to the
antenna is available on the AON pin. An external resistor between PVDD and ISNS is used to set the “antenna short”
and “antenna open” current thresholds. The actual antenna current is derived from the measured voltage drop across
the external sense resistor. The minimum and maximum voltage drop thresholds are internally set to 36mV and 300mV,
respectively. For a 56Ω external sense resistor, these voltage drops correspond to minimum (“antenna open”) and
maximum (“antenna short”) current thresholds
I
min
= 36mV/56Ω = 640µA and I
max
= 300mV/56Ω = 5.35mA.
Once the PT9120 is set to the fully active mode, internal antenna detector circuitry determines whether an active
antenna is properly connected by monitoring the current consumed by the antenna. As long as the monitored current
falls within the range delineated by I
min
and I
max
, the AOK pin is set to logic HIGH, and an internal switch within the
PT9120 is closed to allow voltage to be supplied to the antenna from the AON pin. Otherwise, the AOK pin is set to logic
LOW, and additionally, if the voltage drop across the sense resistor is > 300mV, the output current thru the AON pin is
limited to a value around 10% above I
max
.
If desired, the antenna switch may be bypassed by connecting the active antenna directly to the ISNS pin. Furthermore,
the antenna detector may be bypassed by shorting PVDD to ISNS (AOK will always be set to logic LOW). In both these
cases, the short circuit current-limiting protection circuit is disabled.
If no active antenna is used, PVDD must be connected to ground, while AON and ISNS may be connected to ground or
left open. In this case, the AOK pin will always be set to logic HIGH when the PT9120 is in fully active mode, and will be
set to logic LOW in all other modes.
EXTERNAL LNA
As shown in the application circuit, an off-chip cascade LNA (15dB gain and 1.5dB NF) may be used to amplify the
1575.42MHz L1 GPS RF input signal prior to sending it to the RF input of the PT9120. The input and output impedances
for the LNA are nominally 50Ω at 1575.42MHz.
PRE1.3
5
FPGA/CPLD
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