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K7R161882B-FC16

Description
QDR SRAM, 1MX18, 0.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165
Categorystorage    storage   
File Size210KB,20 Pages
ManufacturerSAMSUNG
Websitehttp://www.samsung.com/Products/Semiconductor/
Download Datasheet Parametric View All

K7R161882B-FC16 Overview

QDR SRAM, 1MX18, 0.5ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, FBGA-165

K7R161882B-FC16 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerSAMSUNG
Parts packaging codeBGA
package instructionLBGA, BGA165,11X15,40
Contacts165
Reach Compliance Codecompliant
ECCN code3A991.B.2.A
Maximum access time0.5 ns
Other featuresPIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)166 MHz
I/O typeSEPARATE
JESD-30 codeR-PBGA-B165
JESD-609 codee0
length17 mm
memory density18874368 bit
Memory IC TypeQDR SRAM
memory width18
Number of functions1
Number of terminals165
word count1048576 words
character code1000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize1MX18
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeLBGA
Encapsulate equivalent codeBGA165,11X15,40
Package shapeRECTANGULAR
Package formGRID ARRAY, LOW PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply1.5/1.8,1.8 V
Certification statusNot Qualified
Maximum seat height1.4 mm
Maximum standby current0.24 A
Minimum standby current1.7 V
Maximum slew rate0.4 mA
Maximum supply voltage (Vsup)1.9 V
Minimum supply voltage (Vsup)1.7 V
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
width15 mm
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Document Title
Preliminary
512Kx36 & 1Mx18 & 2Mx9 & 2Mx8 QDR
TM
II b2 SRAM
512Kx36-bit, 1Mx18-bit, 2Mx9-bit, 2Mx8-bit QDR
TM
II b2 SRAM
Revision History
Rev. No.
0.0
0.1
History
1. Initial document.
1. Change the Boundary scan exit order.
2. Correct the Overshoot and Undershoot timing diagram.
1. Change the JTAG Block diagram
Draft Date
Oct. 17, 2002
Dec. 16, 2002
Remark
Advance
Preliminary
0.2
Dec. 26, 2002
Preliminary
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Dec. 2002
Rev 0.2
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