G12™-p 3.3 V, 4 mA,
5-Volt Tolerant, Fail-Safe,
General Purpose I/O Buffers
Datasheet
LSI Logic Corporation provides the following driver/receiver input/output
(I/O) cells for use as general purpose I/O buffers:
•
•
bd4f5fsls33
bd4puf5fsls33
•
•
bd4puodf5fsls33
bd4puodf5fscls33
The I/O buffers provide off-chip, bidirectional I/O signaling for application-
specific integrated circuit (ASIC) chips implemented in the LSI Logic
G12™-p 0.13
µm
process technology. Functionally similar, the I/O buffers
(Figure
1)
provide an ASIC application with different driver options.
Figure 1
Buffer Block Diagrams
b) bd4puf5fsls33
TN
EN
I/O Pad
IO
CEN
A
T
D
IDDTN
Z
PO
I/O Pad
IO
a) bd4f5fsls33
TN
EN
CEN
A
T
D
IDDTN
Z
PO
PI
PI
c) bd4puodf5fsls33
TN
EN
CEN
A
IDDTN
Z
PO
I/O Pad
IO
d) bd4puodf5fscls33
TN
EN
I/O Pad
A
IDDTN
Z
PO
IO
PI
PI
February 2001
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
1
Features and Benefits
•
•
•
•
•
Up to 20 MHz,
3.3 V I/O operation
5-Volt tolerant
Fail-safe at high voltages
Feedthrough protection
20
µA
maximum leakage current
•
•
•
Minimum 4 mA current drive
into a 40 pF load at 20 MHz
1.8 V internal signaling for
reduced power consumption
Uses one standard I/O slot
Signal Descriptions
Table 1
describes signal connections for all four buffers.
Table 1
I/O Buffer Connections
Signal Direction Description
A
CEN
1
D
2
EN
IN
IN
IN
IN
Data input to I/O buffer driver from ASIC circuitry
Enables I/O buffer operation after power-on
Configures driver operating mode
0 = Normal mode
1 = Disable I/O buffer driver
0 = Power down entire cell
3
1 = Normal mode
NAND-tree parametric test input
Configures driver operating mode
0 = Disable I/O buffer driver
1 = Normal mode
Input/output pad
NAND-tree parametric test output
I/O buffer receiver output to ASIC circuitry
IDDTN IN
PI
T
2
TN
IO
PO
Z
IN
IN
IN
IN/OUT
OUT
OUT
1. Not available in bd4puodf5fscls33
2. Available only in bd4f5fsls33 and bd4puf5fsls33. Refer to
Table 4
for settings.
3. Used for production IDDQ leakage test
2
G12™-p 3.3 V, 4 mA, 5-Volt Tolerant, Fail-Safe, General Purpose I/O Buffers
General Description
The buffers include a receiver, driver, and NAND-tree circuitry to conform
with standard LSI Logic test methodology. The buffers translate signals
between the 1.8 V operating levels of the ASIC core circuitry and the
3.3 V operating levels at the I/O pad. They tolerate high DC and transient
voltages at the I/O pad, are fail safe, and provide feedthrough protection.
Voltage Tolerance
The I/O buffers are 5-volt tolerant. Although the off-chip I/O signaling
normally operates at 3.3 volts, external circuitry may cause higher
voltages, typically upwards of 5 volts, to appear at the chip I/O pad.
Circuit and process techniques ensure that such DC or transient voltages
do not damage the I/O buffer circuitry.
Failure and Feedthrough Protection
In the absence of a V
DD
supply, the I/O buffers are fail-safe and protected
against voltage feedthrough. With high voltage applied to the chip I/O
pad, the I/O buffers can survive without degradation for up to ten years.
Furthermore, with a low, maximum 20
µA
leakage current, the high
voltage can not power up the ASIC through voltage feedthrough.
Functional Description of Receivers
The buffers use the same receiver circuitry. The following truth table
(Table
2)
describes receiver behavior.
Table 2
Receiver Truth Table
Inputs
IDDTN IO
0
1
1
1
1
PI
Z
1
0
1
1
Outputs
PO
0
1
1
0
High Impedance 1
0
1
1
0
0
1
1. Factory IDDQ test setting
G12™-p 3.3 V, 4 mA, 5-Volt Tolerant, Fail-Safe, General Purpose I/O Buffers
3
Functional Description of Drivers
The buffers use similar driver circuitry that produces a minimum of 4 mA
of output drive. The buffers provide options for selecting the driver output
configuration and power-up mode (Table
3).
All the buffers except
bd4f5fsls33
have internal pull-up resistor devices. Preset power-up
modes avoid unpredictable output behavior.
Table 3
I/O Buffer Driver Characteristics
Driver Mode
Pull-Up Power-Up Mode Application
3-State
3-State
Current sinking
logic level 0
3-State
General
General
Power-on
reset
General
I/O Buffer Cell
bd4f5fsls33
bd4puf5fsls33
bd4puodf5fsls33
Dynamically programmable open-drain, None
open-source, or totem-pole output
Dynamically programmable open-drain, Yes,
open-source, or totem-pole output
internal
Open-drain output
Yes,
internal
Yes,
internal
bd4puodf5fscls33 Open-drain output
Driver Output Configuration
With the
bd4f5fsls33
(Figure
1a)
or
bd4puf5fsls33
(Figure
1b)
buffer,
the T and D inputs set a driver output to open-drain, open-source, or
totem-pole mode (Table
4).
An application can hardwire the T and D
inputs, or, to dynamically configure a driver output, it can supply the T
and D inputs from a register.
Table 4
T
0
0
1
1
Driver Output Mode Selection
D
0
1
0
1
Output
Open drain
Totem pole
Totem pole
Open source
4
G12™-p 3.3 V, 4 mA, 5-Volt Tolerant, Fail-Safe, General Purpose I/O Buffers
The
bd4puodf5fsls33
(Figure
1c)
and the
bd4puodf5fscls33
(Figure
1d)
buffers fix the output in the open-drain mode.
Pull-Up Resistor
Except for
bd4f5fsls33,
the buffers include a pull-up resistor, which can
provide from 100
µA
to 500
µA
of current across the specified process,
voltage, and temperature ranges.
Note:
Evaluate the buffer models before simulating a design.
Models provided for some third-party design environments
may not correctly represent or even include the pull-up
resistor.
Power-Up Modes
Each buffer has a defined power-up mode (Table
3)
to avoid
unpredictable output behavior. The
bd4f5fsls33, bd4puf5fsls33,
and
bd4puodf5fsls33
buffers preset the driver output to 3-state or current-
sinking mode upon power up. The
bd4puodf5fscls33
buffer has no
preset power-up mode.
Preset to 3-State (bd4f5fsls33 and bd4puf5fsls33)
At power up, circuitry in the
bd4f5fsls33
and
bd4puf5fsls33
buffers
forces the IO signal at the I/O pad to the high-impedance state. To begin
normal operation, the buffers require the ASIC application to assert CEN
to HIGH.
Preset to Open-Drain (bd4puodf5fsls33)
At power up, circuitry in the
bd4puodf5fsls33
buffer forces the driver
output to open-drain mode. As the driver sinks current, it drives the IO
signal at the I/O pad to LOW. Designed primarily for power-on-reset
applications, the buffer holds circuits connected to the I/O pad in the
LOW reset state until the ASIC application asserts CEN to HIGH, thereby
releasing the buffer to operate normally.
To drive the CEN signal HIGH directly from a source external to the
ASIC, connect CEN to a DDRV type I/O pad for ESD protection and
apply an activation signal. Although this activation signal may reach
3.3 V, a signal limited to1.8 V better matches the normal internal
signaling level, and is therefore preferable.
G12™-p 3.3 V, 4 mA, 5-Volt Tolerant, Fail-Safe, General Purpose I/O Buffers
5
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