CBTU04083
1.8 V, wide bandwidth, 4 differential channel,
2 : 1 multiplexer/demultiplexer switch
Rev. 1 — 16 July 2010
Product data sheet
1. General description
CBTU04083 is an 8-to-4 differential channel multiplexer/demultiplexer switch. The
CBTU04083 can switch four differential signals to one of two locations. Using a unique
design technique, NXP has minimized the impedance of the switch such that the
attenuation observed through the switch is negligible, and also minimized the
channel-to-channel skew as well as channel-to-channel crosstalk, as required by the
high-speed serial interface. CBTU04083 allows expansion of existing high speed ports for
extremely low power.
2. Features and benefits
4 differential channel, 2 : 1 multiplexer/demultiplexer
High-speed signal switching; 8.0 Gbit/s
Low intra-pair skew: 10 ps maximum (between positive and negative bits)
Low inter-pair skew: 35 ps maximum
Low crosstalk:
−30
dB at 4 GHz
Low off-state isolation:
−30
dB at 4 GHz
V
DD
operating range: 1.8 V
±
10 %
ESD tolerance:
6 kV HBM
1 kV CDM
HVQFN42 package
3. Applications
Routing of high-speed differential signals with low signal attenuation
PCIe Gen3
DisplayPort 1.2
USB 3.0
SATA 6 Gbit/s
NXP Semiconductors
CBTU04083
1.8 V, wide bandwidth, 4 differential channel, 2 : 1 MUX/deMUX switch
4. Ordering information
Table 1.
Ordering information
Package
Name
CBTU04083BS
HVQFN42
Description
plastic thermal enhanced very thin quad flat package; no leads;
42 terminals; body 3.5
×
9
×
0.85 mm
Version
SOT1144-1
Type number
5. Functional diagram
A0_P
A0_N
A1_P
A1_N
B0_P
B0_N
B1_P
B1_N
C0_P
C0_N
C1_P
C1_N
A2_P
A2_N
A3_P
A3_N
B2_P
B2_N
B3_P
B3_N
C2_P
C2_N
C3_P
C3_N
SEL
002aae642
Fig 1.
Functional diagram of CBTU04083
CBTU04083
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 1 — 16 July 2010
2 of 14
NXP Semiconductors
CBTU04083
1.8 V, wide bandwidth, 4 differential channel, 2 : 1 MUX/deMUX switch
6. Pinning information
6.1 Pinning
41 GND
39 GND
38 B0_P
37 B0_N
36 B1_P
35 B1_N
34 C0_P
33 C0_N
32 C1_P
31 C1_N
29 B2_P
28 B2_N
27 B3_P
26 B3_N
25 C2_P
GND
(exposed
thermal pad)
V
DD
18
GND 19
V
DD
20
GND 21
24 C2_N
23 C3_P
22 C3_N
002aaf592
42 V
DD
GND
A0_P
A0_N
GND
V
DD
A1_P
A1_N
V
DD
SEL
1
2
3
4
5
6
7
8
9
CBTU04083BS
30 V
DD
GND 10
A2_P 11
A2_N 12
V
DD
13
GND 14
A3_P 15
A3_N 16
GND 17
Transparent top view
Fig 2.
Pin configuration for HVQFN42
6.2 Pin description
Table 2.
Symbol
A0_P
A0_N
A1_P
A1_N
A2_P
A2_N
A3_P
A3_N
B0_P
B0_N
B1_P
B1_N
Pin description
Pin
2
3
6
7
11
12
15
16
38
37
36
35
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
channel 1, port B differential signal input/output
channel 0, port B differential signal input/output
channel 3, port A differential signal input/output
channel 2, port A differential signal input/output
channel 1, port A differential signal input/output
Description
channel 0, port A differential signal input/output
CBTU04083
All information provided in this document is subject to legal disclaimers.
40 V
DD
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 1 — 16 July 2010
3 of 14
NXP Semiconductors
CBTU04083
1.8 V, wide bandwidth, 4 differential channel, 2 : 1 MUX/deMUX switch
Pin description
…continued
Pin
29
28
27
26
34
33
32
31
25
24
23
22
9
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CMOS
operation mode select
single-ended input
SEL = LOW: A
→
B
SEL = HIGH: A
→
C
positive supply voltage, 1.8 V to 2.0 V (± 0.1 V)
supply ground
channel 3, port C differential signal input/output
channel 2, port C differential signal input/output
channel 1, port C differential signal input/output
channel 0, port C differential signal input/output
channel 3, port B differential signal input/output
Description
channel 2, port B differential signal input/output
Table 2.
Symbol
B2_P
B2_N
B3_P
B3_N
C0_P
C0_N
C1_P
C1_N
C2_P
C2_N
C3_P
C3_N
SEL
V
DD
GND
5, 8, 13, 18, 20, power
30, 40, 42
1, 4, 10, 14, 17, power
19, 21, 39, 41,
center pad
7. Functional description
Refer to
Figure 1 “Functional diagram of CBTU04083”.
7.1 Function selection
Table 3.
SEL
LOW
HIGH
Function selection
Function
An to Bn
An to Cn
CBTU04083
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 1 — 16 July 2010
4 of 14
NXP Semiconductors
CBTU04083
1.8 V, wide bandwidth, 4 differential channel, 2 : 1 MUX/deMUX switch
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DD
T
case
V
ESD
Parameter
supply voltage
case temperature
electrostatic discharge voltage
HBM
CDM
[1]
[2]
[1]
[2]
Conditions
Min
−0.5
−40
-
-
Max
+2.5
+85
6000
1000
Unit
V
°C
V
V
Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model -
Component level; Electrostatic Discharge Association, Rome, NY, USA.
Charged Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing, Charged Device
Model - Component level; Electrostatic Discharge Association, Rome, NY, USA.
9. Recommended operating conditions
Table 5.
Symbol
V
DD
V
I
T
amb
Recommended operating conditions
Parameter
supply voltage
input voltage
ambient temperature
operating in free air
Conditions
Min
1.62
−0.5
−40
Typ
1.8
-
-
Max
1.98
V
DD
+85
Unit
V
V
°C
10. Static characteristics
Table 6.
Static characteristics
V
DD
= 1.8 V
±
10 %; T
amb
=
−
40
°
C to +85
°
C; unless otherwise specified.
Symbol
I
DD
I
IH
I
IL
V
IH
V
IL
V
IK
[1]
[2]
Parameter
supply current
HIGH-level input current
LOW-level input current
HIGH-level input voltage
LOW-level input voltage
input clamping voltage
Conditions
V
DD
= max.; V
I
= GND or V
DD
V
DD
= max.; V
I
= V
DD
V
DD
= max.; V
I
= GND
SEL pin
SEL pin
V
DD
= max.; I
I
=
−18
mA
Min
-
-
-
0.65V
DD
−0.5
-
Typ
[1]
-
-
-
-
-
−0.7
Max
4
±5
[2]
±5
[2]
-
0.15V
DD
−1.2
Unit
mA
μA
μA
V
V
V
Typical values are at V
DD
= 1.8 V, T
amb
= 25
°C,
and maximum loading.
Input leakage current is
±50 μA
if differential pairs are pulled to HIGH and LOW.
CBTU04083
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 1 — 16 July 2010
5 of 14
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