PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
LIFE SUPPORT POLICY
Pericom Semiconductor Corporation’s products are not authorized for use as critical components in life support devices or systems
unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of PSC.
1)
Life support devices or system are devices or systems which:
a) Are intended for surgical implant into the body or
b) Support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided
in the labeling, can be reasonably expected to result in a significant injury to the user.
A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to
cause the failure of the life support device or system, or to affect its safety or effectiveness. Pericom Semiconductor Corporation
reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or
performance and to supply the best possible product. Pericom Semiconductor does not assume any responsibility for use of any
circuitry described other than the circuitry embodied in a Pericom Semiconductor product. The Company makes no
representations that circuitry described herein is free from patent infringement or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Pericom
Semiconductor Corporation.
2)
All other trademarks are of their respective companies.
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APRIL 2006 – Revision 1.1
06-0057
PI7C8150A
2-PORT PCI-TO-PCI BRIDGE
TABLE OF CONTENTS
1
2
INTRODUCTION................................................................................................. 11
SIGNAL DEFINITIONS...................................................................................... 12
2.1
S
IGNAL
T
YPES
............................................................................................................................... 12
2.2
S
IGNALS
........................................................................................................................................ 12
2.2.1
PRIMARY BUS INTERFACE SIGNALS
.......................................................................... 12
2.2.3
CLOCK SIGNALS
............................................................................................................... 15
2.2.4
MISCELLANEOUS SIGNALS...........................................................................................
16
2.2.5
GENERAL PURPOSE I/O INTERFACE SIGNALS
........................................................ 17
2.2.6
JTAG BOUNDARY SCAN SIGNALS
................................................................................ 17
2.2.7
POWER AND GROUND.....................................................................................................
17
2.3
PIN LIST – 208-PIN FQFP .......................................................................................................... 18
2.4
PIN LIST – 256-BALL PBGA ..................................................................................................... 20
3
PCI BUS OPERATION........................................................................................ 21
3.1
TYPES OF TRANSACTIONS..................................................................................................... 22
3.2
SINGLE ADDRESS PHASE ....................................................................................................... 22
3.3
DEVICE SELECT (DEVSEL_L) GENERATION ...................................................................... 23
3.4
DATA PHASE ............................................................................................................................. 23
3.5
WRITE TRANSACTIONS .......................................................................................................... 23
3.5.1
MEMORY WRITE TRANSACTIONS................................................................................
23
3.5.2
MEMORY WRITE AND INVALIDATE
............................................................................ 24
3.5.3
DELAYED WRITE TRANSACTIONS...............................................................................
25
3.5.4
WRITE TRANSACTION ADDRESS BOUNDARIES.......................................................
26
3.5.5
BUFFERING MULTIPLE WRITE TRANSACTIONS.....................................................
26
3.5.6
FAST BACK-TO-BACK TRANSACTIONS
....................................................................... 26
3.6
READ TRANSACTIONS............................................................................................................ 27
3.6.1
PREFETCHABLE READ TRANSACTIONS....................................................................
27
3.6.2
NON-PREFETCHABLE READ TRANSACTIONS..........................................................
27
3.6.3
READ PREFETCH ADDRESS BOUNDARIES
............................................................... 28
3.6.4
DELAYED READ REQUESTS
.......................................................................................... 28
3.6.5
DELAYED READ COMPLETION WITH TARGET
........................................................ 29
3.6.6
DELAYED READ COMPLETION ON INITIATOR BUS................................................
29
3.6.7
FAST BACK-TO-BACK READ TRANSACTION
............................................................. 30
3.7
CONFIGURATION TRANSACTIONS ...................................................................................... 30
3.7.1
TYPE 0 ACCESS TO PI7C8150A.......................................................................................
31
3.7.2
TYPE 1 TO TYPE 0 CONVERSION
.................................................................................. 31
3.7.3
TYPE 1 TO TYPE 1 FORWARDING.................................................................................
33
3.7.4
SPECIAL CYCLES
............................................................................................................. 34
3.8
TRANSACTION TERMINATION ............................................................................................. 34
3.8.1
MASTER TERMINATION INITIATED BY PI7C8150A
................................................. 35
3.8.2
MASTER ABORT RECEIVED BY PI7C8150A
................................................................ 36
3.8.3
TARGET TERMINATION RECEIVED BY PI7C8150A..................................................
36
3.8.3.1 DELAYED WRITE TARGET TERMINATION RESPONSE........................................ 37
3.8.3.2 POSTED WRITE TARGET TERMINATION RESPONSE ........................................... 37
3.8.3.3 DELAYED READ TARGET TERMINATION RESPONSE ......................................... 38
3.8.4
TARGET TERMINATION INITIATED BY PI7C8150A..................................................
39
3.8.4.1 TARGET RETRY ............................................................................................................ 39
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APRIL 2006 – Revision 1.1
06-0057
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