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Dual Interface for
Flat Panel Displays
AD9882
FEATURES
Analog Interface
140 MSPS Maximum Conversion Rate
Programmable Analog Bandwidth
0.5 V to 1.0 V Analog Input Range
500 ps p-p PLL Clock Jitter at 140 MSPS
3.3 V Power Supply
Full Sync Processing
Midscale Clamping
4:2:2 Output Format Mode
Digital Interface
DVI 1.0 Compatible Interface
112 MHz Operation
High Skew Tolerance of 1 Full Input Clock
Sync Detect for
“Hot
Plugging”
Supports High Bandwidth Digital Content Protection
APPLICATIONS
RGB Graphics Processing
LCD Monitors and Projectors
Plasma Display Panels
Scan Converter
Microdisplays
Digital TV
FUNCTIONAL BLOCK DIAGRAM
AD9882
ANALOG INTERFACE
8
REF
A/D
R
OUT
REFBYPASS
R
AIN
CLAMP
G
AIN
CLAMP
A/D
8
G
OUT
B
AIN
SOGIN
HSYNC
FILT
VSYNC
CLAMP
A/D
8
B
OUT
8
8
8
R
OUT
G
OUT
B
OUT
DATACK
SYNC
PROCESSING AND
CLOCK
GENERATION
HSOUT
VSOUT
SOGOUT
SCL
SDA
A
0
SERIAL REGISTER AND
POWER MANAGEMENT
MUXES
DATACK
HSOUT
VSOUT
SOGOUT
DE
DIGITAL INTERFACE
R
X0+
R
X0–
R
X1+
R
X1–
R
X2+
R
X2–
R
XC+
R
XC–
R
TERM
DDCSCL
DDCSDA
MCL
MDA
8
DVI
RECEIVER
8
8
R
OUT
G
OUT
B
OUT
DATACK
DE
HSYNC
HDCP
VSYNC
GENERAL DESCRIPTION
The AD9882 offers designers the flexibility of an analog interface
and Digital Visual Interface (DVI) receiver integrated on a single
chip. Also included is support for High bandwidth Digital
Content Protection (HDCP).
Analog Interface
The AD9882 is a complete 8-bit 140 MSPS monolithic analog
interface optimized for capturing RGB graphics signals from
personal computers and workstations. Its 140 MSPS encode
rate capability and full power analog bandwidth of 300 MHz
supports resolutions up to SXGA (1280
¥
1024 at 75 Hz).
The analog interface includes a 140 MHz triple ADC with
internal 1.25 V reference, a Phase Locked Loop (PLL), and
programmable gain, offset, and clamp control. The user provides
only a 3.3 V power supply, analog input, and Hsync. Three-
state CMOS outputs may be powered from 2.2 V to 3.3 V.
The AD9882’s on-chip PLL generates a pixel clock from Hsync.
Pixel clock output frequencies range from 12 MHz to 140 MHz.
PLL clock jitter is typically 500 ps p-p at 140 MSPS. The AD9882
also offers full sync processing for composite sync and Sync-on-
Green (SOG) applications.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
Digital Interface
The AD9882 contains a DVI 1.0 compatible receiver and supports
display resolutions up to SXGA (1280
¥
1024 at 60 Hz). The
receiver features an intra-pair skew tolerance of up to one full
clock cycle.
With the inclusion of HDCP, displays may now receive encrypted
video content. The AD9882 allows for authentication of a video
receiver, decryption of encoded data at the receiver, and renew-
ability of that authentication during transmission as specified by
the HDCP v1.0 protocol.
Fabricated in an advanced CMOS process, the AD9882 is
provided in a space-saving 100-lead LQFP surface-mount plastic
package and is specified over the 0∞C to 70∞C temperature range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
AD9882–SPECIFICATIONS
ANALOG INTERFACE
ELECTRICAL CHARACTERISTICS
Parameter
RESOLUTION
DC ACCURACY
Differential Nonlinearity
Integral Nonlinearity
No Missing Codes
ANALOG INPUT
Input Voltage Range
Minimum
Maximum
Gain Tempco
Input Bias Current
Input Full-Scale Matching
Offset Adjustment Range
REFERENCE OUTPUT
Output Voltage
Temperature Coefficient
SWITCHING PERFORMANCE
1
Maximum Conversion Rate
Minimum Conversion Rate
Data to Clock Skew
Serial Port Timing
t
BUFF
t
STAH
t
DHO
t
DAL
t
DAH
t
DSU
t
STASU
t
STOSU
Hsync Input Frequency
Maximum PLL Clock Rate
Minimum PLL Clock Rate
PLL Jitter
Sampling Phase Tempco
DIGITAL INPUTS
Input Voltage, High (V
IH
)
Input Voltage, Low (V
IL
)
Input Current, High (I
IH
)
Input Current, Low (I
IL
)
Input Capacitance
DIGITAL OUTPUTS
1
Output Voltage, High (V
OH
)
Output Voltage, Low (V
OL
)
Duty Cycle, DATACK
Output Coding
25∞C
Full
25∞C
Full
Full
I
VI
I
VI
VI
(V
D
= 3.3 V, V
DD
= 3.3 V, ADC Clock = Maximum Conversion Rate, unless
otherwise noted.)
AD9882KST-100
Min Typ
Max
8
±
0.5
±
0.5
Guaranteed
+1.25/–1.0
+1.35/–1.0
±
1.85
±
2.0
AD9882KST-140
Typ
Max
8
±
0.5
±
0.5
Guaranteed
+1.35/–1.0
+1.45/–1.0
±
2.0
±
2.3
Test
Temp Level
Min
Unit
Bits
LSB
LSB
LSB
LSB
Full
Full
25∞C
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25∞C
Full
Full
Full
Full
Full
Full
25∞C
Full
Full
Full
VI
VI
V
IV
VI
VI
VI
V
VI
IV
IV
VI
VI
VI
VI
VI
VI
VI
VI
IV
VI
IV
IV
IV
IV
VI
VI
IV
IV
V
IV
IV
IV
0.5
1.0
100
1.5
49
1.25
±
50
1
8.0
56
1.32
1.0
100
1.5
49
1.25
±
50
0.5
46
1.20
46
1.20
1
8.0
56
1.32
V p-p
V p-p
ppm/∞C
mA
% FS
% FS
V
ppm/∞C
MSPS
MSPS
ns
ms
ms
ms
ms
ms
ns
ms
ms
kHz
MHz
MHz
ps p-p
ps p-p
ps/∞C
V
V
mA
mA
pF
V
V
%
100
–0.5
4.7
4.0
0
4.7
4.0
250
4.7
4.0
15
100
500
15
2.6
0.8
–1.0
+1.0
3
V
DD
– 0.1
45
50
Binary
0.4
55
10
+2.0
140
–0.5
4.7
4.0
0
4.7
4.0
250
4.7
4.0
15
140
500
15
2.6
0.8
–1.0
+1.0
3
V
DD
– 0.1
45
50
Binary
0.4
55
10
+2.0
110
12
700
2
1000
2
110
12
700
2
1000
2
–2–
REV. A
AD9882
Parameter
POWER SUPPLY
1
V
D
Supply Voltage
V
DD
Supply Voltage
PV
D
Supply Voltage
I
D
Supply Current (V
D
)
I
DD
Supply Current (V
DD
)
3
IPV
D
Supply Current (PV
D
)
Total Supply Current
Power-Down Supply Current
DYNAMIC PERFORMANCE
Analog Bandwidth, Full Power
Signal-to-Noise Ratio (SNR)
f
IN
= 2.3 MHz
Crosstalk
THERMAL CHARACTERISTICS
4
JA
Junction-to-Ambient
Test
Temp Level
Full
Full
Full
25∞C
25∞C
25∞C
Full
Full
25∞C
25∞C
Full
IV
IV
IV
V
V
V
VI
VI
V
V
V
V
AD9882KST-100
Min
Typ
Max
3.15
2.2
3.15
3.3
3.3
3.3
162
47
19
228
30
300
44
55
43
3.45
3.6
3.45
AD9882KST-140
Min
Typ
Max
3.15
2.20
3.15
3.3
3.3
3.3
181
63
21
265
30
300
43
55
43
3.45
3.6
3.45
Unit
V
V
V
mA
mA
mA
mA
mA
MHz
dB
dBc
∞C/W
237
35
274
35
NOTES
1
Drive Strength = 11.
2
VCO Range = 10, Charge Pump Current = 110, PLL Divider = 1693.
3
DATACK Load = 15 pF, Data Load = 5 pF.
4
Simulated typical performance with package mounted to a four-layer board.
Specifications subject to change without notice.
REV. A
–3–
AD9882
DIGITAL INTERFACE
ELECTRICAL CHARACTERISTICS
Parameter
RESOLUTION
DC DIGITAL I/O Specifications
High Level Input Voltage (V
IH
)
Low Level Input Voltage (V
IL
)
High Level Output Voltage (V
OH
)
Low Level Output Voltage (V
OL
)
Output Leakage Current (I
OL
)
DC SPECIFICATIONS
Output High Drive
(I
OHD
)(V
OUT
= V
OH
)
Output Low Drive
(I
OLD
)(V
OUT
= V
OL
)
DATACK High Drive
(V
OHC
)(V
OUT
= V
OH
)
DATACK Low Drive
(V
OLC
)(V
OUT
= V
OL
)
Differential Input Voltage
Single-Ended Amplitude
POWER SUPPLY
V
D
Supply Voltage
V
DD
Supply Voltage
PV
D
Supply Voltage
I
D
Supply Current (Typical Pattern)
1
I
DD
Supply Current (Typical Pattern)
1, 2
IPV
D
Supply Current (Typical Pattern)
1
Total Supply Current with HDCP
(Typical Pattern)
1, 2
I
D
Supply Current (Worst-Case Pattern)
3
I
DD
Supply Current (Worst-Case Pattern)
2, 3
IPV
D
Supply Current (Worst-Case Pattern)
3
Total Supply Current with HDCP
(Worst-Case Pattern)
2, 3
Power-Down Supply Current (I
PD
)
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25∞C
25∞C
25∞C
Full
25∞C
25∞C
25∞C
Full
Full
VI
VI
IV
IV
IV
V
V
V
V
V
V
V
V
V
V
V
V
IV
IV
IV
IV
V
V
V
IV
V
V
V
IV
VI
75
3.15
2.2
3.15
3.3
3.3
3.3
269
32
54
355
276
127
54
457
30
2.6
0.8
2.4
–10
11
8
5
–7
–6
–5
28
14
7
–15
–9
–7
800
3.45
3.6
3.45
0.4
+10
(V
D
= 3.3 V, V
DD
= 3.3 V, Clock = Maximum, unless otherwise noted.)
Temp
Test
Level
Min
AD9882KST
Typ
Max
8
Unit
Bits
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mV
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
Conditions
High Impedance
Output Drive = High
Output Drive = Med
Output Drive = Low
Output Drive = High
Output Drive = Med
Output Drive = Low
Output Drive = High
Output Drive = Med
Output Drive = Low
Output Drive = High
Output Drive = Med
Output Drive = Low
367
468
35
–4–
REV. A
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