These miniature surface mount MOSFETs utilize High
Cell Density process. Low r
DS(on)
assures minimal
power loss and conserves energy, making this device
ideal for use in power management circuitry. Typical
applications are PWMDC-DC converters, power
management in portable and battery-powered
products such as computers, printers, battery charger,
telecommunication power system, and telephones
power system.
Product Summary
V
DS
(V)
-30
r
DS(on)
(mΩ)
49@V
GS
=-10V
69@V
GS
=-4.5V
I
D
(A)
-5.7
-5.0
Pin Assignments
S
S
S
G
1
2
3
4
8
7
6
5
Pin Descriptions
D
D
D
D
Pin Name
S
G
D
Description
Source
Gate
Drain
SOP-8
Ordering information
A X
Feature
F :MOSFET
PN
9435P X X X
Package
S: SOP-8
Lead Free
Blank : Normal
L : Lead Free Package
Packing
Blank : Tube or Bulk
A : Tape & Reel
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of
this product. No rights under any patent accompany the sale of the product.
Rev. 1.1 Jul 20, 2004
1/5
AF9435P
P-Channel 30-V (D-S) MOSFET
Absolute Maximum Ratings
(T
A
=25ºC unless otherwise noted)
Symbol
V
DS
V
GS
I
D
I
DM
I
S
P
D
T
J
, T
STG
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
(Note 1)
T
A
=25ºC
T
A
=70ºC
Pulsed Drain Current
(Note 2)
Continuous Source Current (Diode Conduction)
(Note 1)
T
A
=25ºC
Power Dissipation
(Note 1)
T
A
=70ºC
Operating Junction and Storage Temperature Range
Rating
-30
±25
±6.5
±5.2
±30
-1.6
3.1
2.0
-55 to 150
Units
V
V
A
A
A
W
ºC
Thermal Resistance Ratings
Symbol
R
θJC
R
θJA
Parameter
Maximum Junction-to-Case
(Note 1)
Maximum Junction-to-Ambient
(Note 1)
t
<
5 sec
t
<
5 sec
Maximum
25
40
Units
ºC/W
ºC/W
Note 1:
surface Mounted on 1”x 1” FR4 Board.
Note 2:
Pulse width limited by maximum junction temperature
Specifications
(T
A
=25ºC unless otherwise noted)
Symbol
Static
V
(BR)DSS
V
GS(th)
I
GSS
I
DSS
I
D(on)
r
DS(on)
Parameter
Drain-Source breakdown Voltage
Gate-Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Current
(Note 3)
Drain-Source On-Resistance
(Note 3)
Test Conditions
V
GS
=0V, I
D
=-250uA
V
DS
= V
GS
, I
D
=-250uA
V
DS
=0V, V
GS
=±25V
V
DS
=-24V, V
GS
=0V
V
DS
=-24V, V
GS
=0V,
T
J
=55ºC
V
DS
=-5V, V
GS
=-10V
V
GS
=-10V, I
D
=-5.7A
V
GS
=-4.5V, I
D
=-5.0A
V
GS
=-10V, I
D
=-5.7A,
T
J
=55ºC
V
DS
=-15V, I
D
=-5.7A
I
S
=-2.1A, V
GS
=0V
V
DS
=-15V, V
GS
=-4.5V,
I
D
=-5.7A
Min.
-30
-1
-
-
-
-30
-
-
-
-
-
-
-
-
-
-
-
-
Limits
Typ.
-
-1.6
-
-
-
-
38
54
42
19
-0.7
6
2.0
2.7
7
13
14
9
Max.
-
-3
±100
-1
-5
-
49
69
54
-
-1.2
11
-
-
14
24
25
17
S
V
Unit
V
V
nA
uA
A
mΩ
g
fs
Forward Tranconductance
(Note 3)
V
SD
Diode Forward Voltage
Dynamic
(Note 4)
Q
g
Total Gate Charge
Q
gs
Gate-Source Charge
Q
gd
Gate-Drain Charge
Switching
t
d(on)
Turn-On Delay Time
t
r
Rise Time
t
d(off)
Turn-Off Delay Time
t
f
Fall-Time
nC
V
DD
=-15, R
L
=15Ω,
I
D
=-1A, V
GEN
=-10V,
R
G
=6Ω
nS
Note 3:
Pulse test: PW
<
300us duty cycle
<
2%.
Note 4:
Guaranteed by design, not subject to production testing.
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