LE28F4001M-20 datasheet, PDF - EEWORLD Datasheet

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LE28F4001M-20: DescriptionIC IC,EEPROM,NOR FLASH,512KX8,CMOS,SOP,32PIN,PLASTIC, Programmable ROM; Categorystorage storage; File Size218KB，14 Pages; ManufacturerON Semiconductor; Websitehttp://www.onsemi.cn

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LE28F4001M-20 Overview

IC IC,EEPROM,NOR FLASH,512KX8,CMOS,SOP,32PIN,PLASTIC, Programmable ROM

LE28F4001M-20 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	ON Semiconductor
package instruction	SOP-32
Reach Compliance Code	compliant
Maximum access time	200 ns
command user interface	NO
Data polling	YES
Durability	10000 Write/Erase Cycles
JESD-30 code	R-PDSO-G32
length	20.7 mm
memory density	4194304 bit
Memory IC Type	FLASH
memory width	8
Number of functions	1
Number of departments/size	2K
Number of terminals	32
word count	524288 words
character code	512000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512KX8
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP32,.55
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	PARALLEL
power supply	5 V
Programming voltage	5 V
Certification status	Not Qualified
Maximum seat height	3.1 mm
Department size	256
Maximum standby current	0.00002 A
Maximum slew rate	0.04 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
switch bit	YES
type	NOR TYPE
width	11.2 mm

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Ordering number : EN*5239A

CMOS LSI

LE28F4001M, T, R-15/20

4 MEG (524288 words

8 bits) Flash Memory

Preliminary

Overview

The LE28F4001 Series ICs are 524288-word

8-bit flash

memory products that support on-board reprogramming

and feature 5 V single-voltage power supply operation.

CMOS peripheral circuits were adopted for high speed,

low power, and ease of use. These products support a

sector (256 bytes) erase function for fast data rewriting.

Package Dimensions

unit: mm

3205-SOP32

[LE28F4001M]

Features

• Fabricated in a highly reliable 2-layer polysilicon

CMOS flash EEPROM process.

• Read and write operation from a 5 V single-voltage

power supply

• Sector erase function: 256 bytes per sector

• Fast access time: 150/200 ns

• Low power

— Operating current (read): 25 mA (maximum)

— Standby current: 20 µA (maximum)

• Highly reliable read and write operations

— Sector write cycles: 10

cycles

— Data retention time: 10 years

• Address and data latches

• Self-timer erase and programming

• Byte programming time: 35 µs (maximum)

• Write complete detection: Toggle bit and data polling

• Hardware and software data protection

• Pin assignment conforms to the JEDEC byte-wide

EEPROM standard

• Packages

SOP 32-pin (525 mil) plastic package

:LE28F4001M

TSOP 40-pin (10

14 mm) plastic package :LE28F4001T

TSOP 40-pin (10

14 mm) plastic package :LE28F4001R

SANYO: SOP32

unit: mm

3087A-TSOP40

[LE28F4001T, R]

SANYO: TSOP40 (TYPE-I)

These FLASH MEMORY products incorporate technology licensed Silicon Storage Technology, Inc.

SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

63096HA (OT) No. 5239-1/14

LE28F4001M, T, R-15/20

Notes on Command Settings

Type definitions: X = Don’t care

Address definitions: SA = Sector Address = A18 to A8; sector size = 256 bytes; A7 to A0 = X for this command.

Address definitions: PA = Program Address = A18 to A0.

Data definition: PD = Program Data, H = number in hex.

SDP = Software Data Protect mode using 7-read-cycle sequence.

Y = the operation can be executed with software data protect enabled. N = the operation cannot be executed with

software data protect enabled.

6. Refer to figures 9 and 10 for the 7-read-cycle sequence software data protection.

7. Address 0000H retrieves the manufacturer code of BF (hex), address 0001H retrieves the device code of 04 (hex).

Product Overview

The LE28F4001 Series products are EEPROMs that support sector erase and byte programming functions and that

feature a 512K

8 organization. These products support both erase and programming from a 5-V single-voltage power

supply, conform to the JEDEC standards for byte-wide memory pin assignments, and are pin compatible with industry

standard EPROMs, flash EPROMs, and EEPROMs.

The LE28F4001 Series products, provide a 35 µs maximum byte programming time and a 4 ms sector erase time.

Programming and erase operations can both be optimized by using the toggle bit and Data polling functions that indicate

the completion of the write cycle. To protect data against unintentional writes, these products provide both hardware and

software data protection schemes. The LE28F4001 Series products, guarantee 10

sector write cycles. The data retention

time is ten years or longer.

The LE28F4001 Series functional block diagram and the 40-pin TSOP and 32-pin SOP package pin assignments are

shown on page 2, and the pin functions and command settings are listed on page 3.

Device Operation

Commands are used to execute the device’s memory functions. Commands are written to the command register with

standard microprocessor write timing. Commands are written by setting WE low while CE is held low. The address is

latched on the falling edge of either CE or WE, whichever occurs later. Data is latched on the rising edge of either CE or

WE, whichever occurs first. However, the address is latched on the rising edge of either OE or CE, whichever occurs

first during the software write protect sequence.

Command Definition

The “Command Settings” section provided an overview and list of the LE28F4001 commands. This section describes the

functions provided by those commands in detail.

Before executing the LE28F4001 Series byte programming or erase functions, the application system must execute the

software data unprotect sequence.

No. 5239-4/14

LE28F4001M, T, R-15/20

1. Sector erase operation

The sector erase operation consists of a setup command and an execute command. The setup commands sets the

device to a state where all the bytes in the sector can be erased electrically. A single sector has 256 bytes. Since

almost all applications use erase operations that are not whole-chip erase operations but rather are single sector erase

operations, this sector erase function significantly increases the flexibility and ease of use of the LE28F4001 Series.

The setup command is executed by writing 20H to the command register.

An execute command (D0H) must be written to the command register to execute the sector erase operation. The

sector erase operation starts on the rising edge of the WE pulse and is automatically completed under internal timing

control. Figure 6 shows the timing waveforms for this operation.

This two stage sequence in which a setup command and a following execute command are required guarantees that

the memory at the sector specified by the address data will not be erased accidentally.

2. Sector erase flowchart

The quick and reliable erasure of up to 256 bytes of memory can be achieved by following the sector erase flowchart

shown in Figure 1. The whole operation consists of executing two commands. A sector erase operation completes in

a maximum of 4 ms. Although the erase operation can be completed by executing a reset operation, the sector may

not be completely erased if that reset is executed before the 4 ms time out period elapses. The erase command can be

re-executed as many times as required before the erase completes. Excessive erasure cannot cause problems with the

LE28F4001 Series products.

3. Byte programming operation

The byte programming operation is started by writing a setup command (10H) to the command register.

Once the setup command is executed, the execute command is started by the next WE pulse transition. Figure 7

shows the timing waveforms for this operation. The address and the data are latched internally on the falling edge

and rising edge of the WE pulse, respectively. The WE rising edge also corresponds to the start of the programming

operation. The programming operation is automatically completed under internal timing control. Figures 2 and 7

show the programming characteristics and waveforms.

As mentioned previously, this two stage sequence in which a setup command and a following execute operation are

required guarantees that the memory cells will not be programmed accidentally.

4. Byte programming flowchart

Figure 2 shows the device data programming operation. This is effected by following the byte programming

flowchart. The byte programming command sets up the byte to be written. The address is latched on the falling edge

of WE or CE, whichever is later. The data bus is latched on the rising edge of WE or CE, whichever is earlier, and

the programming operation starts at that point. The completion of the write operation can be detected using either the

toggle bit or by polling a Data pin.

5. Reset operation

The reset command is a procedure for safely terminating an erase or programming command sequence. Writing FFH

to the command register after issuing an erase or programming setup command will safely cancel that operation. The

contents of memory will not be changed. The device goes to read mode after executing a reset command. The reset

command cannot activate the software data protect function. Figure 8 shows the timing waveforms.

6. Read operation

A read operation is performed by setting CE and OE, and then WE, to read mode. Figure 3 shows the read mode

timing waveforms, and the read mode conditions are shown as “functional logic”. A read cycle from the host

searches for the memory array data. The device remains in the read state until another command is written to the

command register.

As a default, the device will be in read mode in the write protect state from the time power is first applied until a

command is written to the command register. The unprotect sequence must be executed to perform a write operation

(erase or programming).

The read operation is controlled by CE and OE, and both must be set to the logic low level to activate the read

function. When CE is at the logic high level, the chip is in the unselected state and only draws the standby current.

OE controls the output pins. The device output pins will be in the high-impedance state if either CE or OE is at the

logic high level.

No. 5239-5/14

LE28F4001M-20 Related Products

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Description	IC IC,EEPROM,NOR FLASH,512KX8,CMOS,SOP,32PIN,PLASTIC, Programmable ROM	IC,EEPROM,NOR FLASH,512KX8,CMOS,SOP,32PIN,PLASTIC	IC,EEPROM,NOR FLASH,512KX8,CMOS,TSSOP,40PIN,PLASTIC	IC,EEPROM,NOR FLASH,512KX8,CMOS,TSSOP,40PIN,PLASTIC	IC,EEPROM,NOR FLASH,512KX8,CMOS,TSSOP,40PIN,PLASTIC	IC,EEPROM,NOR FLASH,512KX8,CMOS,TSSOP,40PIN,PLASTIC
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	ON Semiconductor	ON Semiconductor	ON Semiconductor	ON Semiconductor	ON Semiconductor	ON Semiconductor
package instruction	SOP-32	SOP-32	TSOP1-40	TSOP1-40	TSOP1-40	TSOP1-40
Reach Compliance Code	compliant	compliant	compliant	not_compliant	compliant	compliant
Maximum access time	200 ns	150 ns	150 ns	200 ns	200 ns	150 ns
command user interface	NO	NO	NO	NO	NO	NO
Data polling	YES	YES	YES	YES	YES	YES
Durability	10000 Write/Erase Cycles	10000 Write/Erase Cycles	10000 Write/Erase Cycles	10000 Write/Erase Cycles	10000 Write/Erase Cycles	10000 Write/Erase Cycles
JESD-30 code	R-PDSO-G32	R-PDSO-G32	R-PDSO-G40	R-PDSO-G40	R-PDSO-G40	R-PDSO-G40
length	20.7 mm	20.7 mm	12.4 mm	12.4 mm	12.4 mm	12.4 mm
memory density	4194304 bit	4194304 bit	4194304 bit	4194304 bit	4194304 bit	4194304 bit
Memory IC Type	FLASH	FLASH	FLASH	FLASH	FLASH	FLASH
memory width	8	8	8	8	8	8
Number of functions	1	1	1	1	1	1
Number of departments/size	2K	2K	2K	2K	2K	2K
Number of terminals	32	32	40	40	40	40
word count	524288 words	524288 words	524288 words	524288 words	524288 words	524288 words
character code	512000	512000	512000	512000	512000	512000
Operating mode	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
organize	512KX8	512KX8	512KX8	512KX8	512KX8	512KX8
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	SOP	TSOP1	TSOP1	TSOP1	TSOP1
Encapsulate equivalent code	SOP32,.55	SOP32,.55	TSSOP40,.56,20	TSSOP40,.56,20	TSSOP40,.56,20	TSSOP40,.56,20
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
power supply	5 V	5 V	5 V	5 V	5 V	5 V
Programming voltage	5 V	5 V	5 V	5 V	5 V	5 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	3.1 mm	3.1 mm	1.23 mm	1.23 mm	1.23 mm	1.23 mm
Department size	256	256	256	256	256	256
Maximum standby current	0.00002 A	0.00002 A	0.00002 A	0.00002 A	0.00002 A	0.00002 A
Maximum slew rate	0.04 mA	0.04 mA	0.04 mA	0.04 mA	0.04 mA	0.04 mA
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	1.27 mm	1.27 mm	0.5 mm	0.5 mm	0.5 mm	0.5 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
switch bit	YES	YES	YES	YES	YES	YES
type	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE	NOR TYPE
width	11.2 mm	11.2 mm	10 mm	10 mm	10 mm	10 mm

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