XC2V8000-5BF957C datasheet, PDF

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XC2V8000-5BF957C: DescriptionFPGA, 1280 CLBS, 1000000 GATES, 650 MHz, PBGA575; CategoryProgrammable logic devices Programmable logic; File Size88KB，7 Pages; ManufacturerXILINX; Websitehttps://www.xilinx.com/

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XC2V8000-5BF957C Overview

FPGA, 1280 CLBS, 1000000 GATES, 650 MHz, PBGA575

XC2V8000-5BF957C Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	XILINX
Parts packaging code	BGA
package instruction	1.27 MM PITCH, FLIP CHIP, BGA-957
Contacts	957
Reach Compliance Code	not_compliant
ECCN code	3A001.A.7.A
maximum clock frequency	750 MHz
Combined latency of CLB-Max	0.39 ns
JESD-30 code	S-PBGA-B957
JESD-609 code	e0
length	40 mm
Humidity sensitivity level	4
Configurable number of logic blocks	11648
Equivalent number of gates	8000000
Number of entries	1108
Number of logical units	11648
Output times	1108
Number of terminals	957
Maximum operating temperature	85 °C
Minimum operating temperature
organize	11648 CLBS, 8000000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	HBGA
Encapsulate equivalent code	BGA957,31X31,50
Package shape	SQUARE
Package form	GRID ARRAY, HEAT SINK/SLUG
Peak Reflow Temperature (Celsius)	225
power supply	1.5,1.5/3.3,3.3 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	3.5 mm
Maximum supply voltage	1.575 V
Minimum supply voltage	1.425 V
Nominal supply voltage	1.5 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	Tin/Lead (Sn63Pb37)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	40 mm

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Virtex-II 1.5V

Field-Programmable Gate Arrays

DS031-1 (v1.7) October 2, 2001

Advance Product Specification

Summary of Virtex

-II Features

•

Industry First Platform FPGA Solution

IP-Immersion™ Architecture

- Densities from 40K to 8M system gates

- 420 MHz internal clock speed (Advance Data)

- 840+ Mb/s I/O (Advance Data)

SelectRAM™ Memory Hierarchy

- 3 Mb of True Dual-Port™ RAM in 18-Kbit block

SelectRAM resources

- Up to 1.5 Mb of distributed SelectRAM resources

- High-performance interfaces to external memory

DDR-SDRAM interface

FCRAM interface

QDR™-SRAM interface

Sigma RAM interface

Arithmetic Functions

- Dedicated 18-bit x 18-bit multiplier blocks

- Fast look-ahead carry logic chains

Flexible Logic Resources

- Up to 93,184 internal registers / latches with Clock

Enable

- Up to 93,184 look-up tables (LUTs) or cascadable

16-bit shift registers

- Wide multiplexers and wide-input function support

- Horizontal cascade chain and Sum-of-Products

support

- Internal 3-state bussing

High-Performance Clock Management Circuitry

- Up to 12 DCM (Digital Clock Manager) modules

Precise clock de-skew

Flexible frequency synthesis

High-resolution phase shifting

- 16 global clock multiplexer buffers

Active Interconnect™ Technology

- Fourth generation segmented routing structure

- Predictable, fast routing delay, independent of

fanout

SelectI/O-Ultra™ Technology

- Up to 1,108 user I/Os

- 19 single-ended standards and six differential

standards

- Programmable sink current (2 mA to 24 mA) per I/O

Digitally Controlled Impedance (DCI) I/O: on-chip

termination resistors for single-ended I/O standards

- PCI-X @ 133 MHz, PCI @ 66 MHz and 33 MHz

compliance, and CardBus compliant

- Differential Signaling

840 Mb/s Low-Voltage Differential Signaling I/O

(LVDS) with current mode drivers

Bus LVDS I/O

Lightning Data Transport (LDT) I/O with current

driver buffers

Low-Voltage Positive Emitter-Coupled Logic

(LVPECL) I/O

Built-in DDR Input and Output registers

- Proprietary high-performance SelectLink™

Technology

High-bandwidth data path

Double Data Rate (DDR) link

Web-based HDL generation methodology

Supported by Xilinx Foundation™ and Alliance™

Series Development Systems

- Integrated VHDL and Verilog design flows

- Compilation of 10M system gates designs

- Internet Team Design (ITD) tool

SRAM-Based In-System Configuration

- Fast SelectMAP™ configuration

- Triple Data Encryption Standard (DES) security

option (Bitstream Encryption)

- IEEE1532 support

- Partial reconfiguration

- Unlimited re-programmability

- Readback capability

0.15 µm 8-Layer Metal process with 0.12 µm

high-speed transistors

1.5 V (V

CCINT

) core power supply, dedicated 3.3 V

CCAUX

auxiliary and V

CCO

I/O power supplies

IEEE 1149.1 compatible boundary-scan logic support

Flip-Chip and Wire-Bond Ball Grid Array (BGA)

packages in three standard fine pitches (0.80mm,

1.00mm, and 1.27mm)

100% factory tested

•

http://www.xilinx.com/legal.htm.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS031-1 (v1.7) October 2, 2001

Advance Product Specification

www.xilinx.com

1-800-255-7778

Module 1 of 4

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