K7P403666A
K7P401866A
FEATURES
• 128Kx36 or 256Kx18 Organizations.
• 2.5V Core/1.5V Output Power Supply.
• HSTL Input and Output Levels.
• Differential, HSTL Clock Inputs K, K.
• Synchronous Read and Write Operation
• Registered Input and Registered Output
• Internal Pipeline Latches to Support Late Write.
• Byte Write Capability(four byte write selects, one for each 9bits)
• Synchronous or Asynchronous Output Enable.
• Power Down Mode via ZZ Signal.
• Programmable Impedance Output Drivers.
• JTAG 1149.1 Compatible Test Access port.
• 119(7x17)Pin Ball Grid Array Package(14mmx22mm).
128Kx36 & 256Kx18 SRAM
128Kx36 & 256Kx18 Synchronous Pipelined SRAM
Organization
Part Number
K7P403666A-H30
128Kx36
K7P403666A-H27
K7P403666A-H25
K7P401866A-H30
256Kx18
K7P401866A-H27
K7P401866A-H25
Cycle
Time
3.3
3.6
4.0
3.3
3.6
4.0
Access
Time
1.8
1.9
2.0
1.8
1.9
2.0
FUNCTIONAL BLOCK DIAGRAM
SA[0:16] or SA[0:17]
CK
SS
SW
Latch
SWx
Register
SWx
Register
Latch
SW
Register
SW
Register
Read
Address
Register
1
Write
Address
Register
0
Row Decoder
128Kx36
or
256Kx18
Array
Column Decoder
Write/Read Circuit
SWx
(x=a, b, c, d)
or (x=a, b)
0
1
Data In
Register
SS
Register
SS
Register
Data Out
Register
G
ZZ
K
K
CK
DQx[1:9]
(x=a, b, c, d)
or (x=a, b)
PIN DESCRIPTION
Pin Name
K, K
SAn
DQn
SW
SWa
SWb
SWc
SWd
ZZ
V
DD
V
DDQ
Pin Description
Differential Clocks
Synchronous Address Input
Bi-directional Data Bus
Synchronous Global Write Enable
Synchronous Byte a Write Enable
Synchronous Byte b Write Enable
Synchronous Byte c Write Enable
Synchronous Byte d Write Enable
Asynchronous Power Down
Core Power Supply
Output Power Supply
Pin Name
V
REF
M
1
, M
2
G
SS
TCK
TMS
TDI
TDO
ZQ
V
SS
NC
Pin Description
HSTL Input Reference Voltage
Read Protocol Mode Pins ( M
1
=V
SS
, M
2
=V
DD
)
Asynchronous Output Enable
Synchronous Select
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
Output Driver Impedance Control
GND
No Connection
-2-
Rev 1.0
Nov. 1999
K7P403666A
K7P401866A
FUNCTION DESCRIPTION
128Kx36 & 256Kx18 SRAM
The K7P403666A andK7P401866A are 4,718,592 bit Synchronous Pipeline Mode SRAM. It is organized as 131,072 words of 36
bits(or 262,144 words of 18 bits)and is implemented in SAMSUNG′s advanced CMOS technology.
Single differential HSTL level K clocks are used to initiate the read/write operation and all internal operations are self-timed. At the
rising edge of K clock, All addresses, Write Enables, Synchronous Select and Data Ins are registered internally. Data outs are
updated from output registers edge of the next rising edge of the K clock. An internal write data buffer allows write data to follow one
cycle after addresses and controls. The package is 119(7x17) Ball Grid Array with balls on a 1.27mm pitch.
Read Operation
During reads, the address is registered during the frist clock edge, the internal array is read between this first edge and the second
edge, and data is captured in the output register and driven to the CPU during the second clock edge. SS is driven low during this
cycle, signaling that the SRAM should drive out the data.
During consecutive read cycles where the address is the same, the data output must be held constant without any glitches. This
characteristic is because the SRAM will be read by devices that will operate slower than the SRAM frequency and will require multi-
ple SRAM cycles to perform a single read operation.
Write(Store) Operation
All addresses and SW are sampled on the clock rising edge. SW is low on the rising clock. Write data is sampled on the rising clock,
one cycle after write address and SW have been sampled by the SRAM. SS will be driven low during the same cycle that the
Address, SW and SW[a:d] are valid to signal that a valid operation is on the Address and Control Input.
Pipelined write are supported. This is done by using write data buffers on the SRAM that capture the write addresses on one write
cycle, and write the array on the next write cycle. The "next write cycle" can actually be many cycles away, broken by a series of
read cycles. Byte writes are supported. The byte write signals SW[a:d] signal which 9-bit bytes will be writen. Timing of SW[a:d] is
the same as the SW signal.
Bypass Read Operation
Since write data is not fully written into the array on first write cycle, there is a need to sense the address in case a future read is to be
done from the location that has not been written yet. For this case, the address comparator check to see if the new read address is
the same as the contents of the stored write address Latch. If the contents match, the read data must be supplied from the stored
write data latch with standard read timing. If there is no match, the read data comes from the SRAM array. The bypassing of the
SRAM array occurs on a byte by byte basis. If one byte is written and the other bytes are not, read data from the last written will have
new byte data from the write data buffer and the other bytes from the SRAM array.
Programmable Impedance Output Buffer Operation
This HSTL Late Write SRAM has been designed with programmable impedance output buffers. The SRAMs output buffer impedance
can be adjusted to match the system data bus impedance, by connecting a external resistor (RQ) between the ZQ pin of the SRAM
and V
SS
. The value of RQ must be five times the value of the intended line impedance driven by the SRAM. For example, a 250
Ω
resistor will give an output buffer impedance of 50
Ω
. The allowable range of RQ is from 175
Ω
to 350
Ω
. Internal circuits evaluate and
periodically adjust the output buffer impedance, as the impedance is affected by drifts in supply voltage and temperature. One evalu-
ation occurs every 32 clock cycles, with each evaluation moving the output buffer impedance level only one step at a time toward the
optimum level. Impedance updates occur when the SRAM is in High-Z state, and thus are triggered by write and deselect operations.
Updates will also be triggered with G HIGH initiated High-Z state, providing the specified G setup and hold times are met. Impedance
match is not instantaneous upon power-up. In order to guarantee optimum output driver impedance, the SRAM requires a minimum
number of non-read cycles (1,024) after power-up. The output buffers can also be programmed in a minimum impedance configura-
tion by connecting ZQ to V
SS
or V
DD
.
Mode Control
There are two mode control select pins (M
1
and M
2
) used to set the proper read protocol. This SRAM supports single clock pipelined
operating mode. For proper specified device operation, M
1
must be connected to V
SS
and M
2
must be connected to V
DD
. These
mode pins must be set at power-up and must not change during device operation.
Power-Up/Power-Down Supply Voltage Sequencing
The following power-up supply voltage application is recommended: V
SS
, V
DD
, V
DDQ
, V
REF
, then V
IN
. V
DD
and V
DDQ
can be applied
simultaneously, as long as V
DDQ
does not exceed V
DD
by more than 0.5V during power-up. The following power-down supply voltage
removal sequence is recommended: V
IN
, V
REF
, V
DDQ
, V
DD
, V
SS
. V
DD
and V
DDQ
can be removed simultaneously, as long as V
DDQ
does not exceed V
DD
by more than 0.5V during power-down.
Sleep Mode
Sleep mode is a low power mode initiated by bringing the asynchronous ZZ pin high. During sleep mode, all other inputs are ignored
and outputs are brought to a High-Impedance state. Sleep mode current and output High-Z are guaranteed after the specified sleep
mode enable time. During sleep mode the memory array data content is preserved. Sleep mode must not be initiated until after all
pending operations have completed, as any pending operation is not guaranteed to properly complete after sleep mode is initiated.
Normal operations can be resumed by bringing the ZZ pin low, but only after the specified sleep mode recovery time.
-4-
Rev 1.0
Nov. 1999
K7P403666A
K7P401866A
TRUTH TABLE
K
X
X
↑
↑
↑
↑
↑
↑
↑
↑
ZZ
H
L
L
L
L
L
L
L
L
L
G
X
H
L
L
X
X
X
X
X
X
SS
X
X
H
L
L
L
L
L
L
L
SW
X
X
X
H
L
L
L
L
L
L
SWa
X
X
X
X
H
L
H
H
H
L
SWb
X
X
X
X
H
H
L
H
H
L
SWc
X
X
X
X
H
H
H
L
H
L
SWd
X
X
X
X
H
H
H
H
L
L
DQa
Hi-Z
Hi-Z
Hi-Z
D
OUT
Hi-Z
D
IN
Hi-Z
Hi-Z
Hi-Z
D
IN
128Kx36 & 256Kx18 SRAM
DQb
Hi-Z
Hi-Z
Hi-Z
DQc
Hi-Z
Hi-Z
Hi-Z
DQd
Operation
Hi-Z Power Down Mode. No Operation
Hi-Z Output Disabled.
Hi-Z Output Disabled. No Operation
D
OUT
D
OUT
D
OUT
Read Cycle
Hi-Z
Hi-Z
D
IN
Hi-Z
Hi-Z
D
IN
Hi-Z
Hi-Z
Hi-Z
D
IN
Hi-Z
D
IN
Hi-Z No Bytes Written
Hi-Z Write first byte
Hi-Z Write second byte
Hi-Z Write third byte
D
IN
D
IN
Write fourth byte
Write all byte
ABSOLUTE MAXIMUM RATINGS
Parameter
Core Supply Voltage Relative to V
SS
Output Supply Voltage Relative to V
SS
Voltage on any I/O pin Relative to V
SS
Output Short-Circuit Current
Operating Temperature
Storage Temperature
Symbol
V
DD
V
DDQ
V
TERM
I
OUT
T
OPR
T
STG
Value
-0.5 to 3.0
-0.5 to 3.0
-0.5 to V
DD
+0.5
25
0 to 70
-55 to 125
Unit
V
V
V
mA
°C
°C
Note
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Core Power Supply Voltage
Output Power Supply Voltage
Input High Level
Input Low Level
Input Reference Voltage
Clock Input Signal Voltage
Clock Input Differential Voltage
Clock Input Common Mode Voltage
Symbol
V
DD
V
DDQ
V
IH
V
IL
V
REF
V
IN
-CLK
V
DIF
-CLK
V
CM
-CLK
Min
2.35
1.4
V
REF
+0.1
-0.3
0.6
-0.3
0.1
0.6
Typ
2.5
1.5
-
-
V
DDQ
/2
-
-
V
DDQ
/2
Max
2.65
1.6
V
DDQ
+0.3
V
REF
-0.1
2V
DDQ
/3
V
DDQ
+0.3
V
DDQ
+0.6
2V
DDQ
/3
Unit
V
V
V
V
V
V
V
V
Note
-5-
Rev 1.0
Nov. 1999
FPGA/CPLD
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