K9S5608V0B/A
K9S2808V0B/A
Document Title
K9S6408V0C/B
SmartMedia
TM
SmartMedia
TM
Card
Revision History
Revision No
0.0
0.1
History
Initial issue
1. Explain how pointer operation works in detail.
2. Updated operation for tRST timing
- If reset command(FFh) is written at Ready state, the device goes
into Busy for maximum 5us.
1. Renamed the 17th pin from Vcc to LVD(Low Voltage Detect)
-The LVD is used to electrically detect the proper supply voltage.
By connecting this pin to Vss through a pull-down resister, it is pos-
sible to distinguish 3.3V product from 5V product. When 3.3V is
applied as Vcc to pins 12 and 22, a High’level can be detected
’
on the system side if the device is a 3.3V product, and Low’level
’
for 5V product.
1.Powerup sequence is added
Recovery time of minimum 1µs is required before internal circuit gets
ready for any command sequences
~ 2.5V
Draft Date
July 17th 2000
Nov. 20th 2000
Remark
Advanced
Information
Preliminary
0.2
Mar. 2th 2001
Final
0.3
Sep. 7th 2001
≈
~ 2.5V
V
CC
High
WP
1
µs
WE
2. AC parameter tCLR(CLE to RE Delay, min 50ns) is added.
3. AC parameter tAR1 value : 100ns --> 20ns
Note : For more detailed features and specifications including FAQ, please refer to Samsung’ Flash web site.
s
http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you
have any questions, please contact the SAMSUNG branch office near your office.
≈
1
K9S5608V0B/A
K9S2808V0B/A
Revision History
Revision No
0.4
K9S6408V0C/B
SmartMedia
TM
Draft Date
Sep. 7th 2001
History
1. Unified access timing parameter definition for multiple operating modes
- Changed AC characteristics (Before)
Parameter
ALE to RE Delay (ID read)
ALE to RE Delay (Read cycle)
RE Low to Status Output
CE Low to Status Output
RE access time(Read ID)
- AC characteristics (After)
. Deleted t
RSTO,
t
CSTO
and t
READID
/ Added t
CLR,
t
CEA
Parameter
ALE to RE Delay (ID read)
ALE to RE Delay (Read cycle)
CLE to RE Delay
CE Access Time
Symbol
t
AR1
t
AR2
t
CLR
t
CEA
Min
50
50
10
-
45
Max
-
-
ns
Unit
Symbol
t
AR1
t
AR2
t
RSTO
t
CSTO
t
READID
Min
100
100
-
-
-
Max
-
-
35
45
35
ns
Unit
Remark
Final
CLE
tCR
CE
WE
tAR
ALE
RE
tREA
I/O
0
~
7
90h
00h
Address. 1cycle
ECh
Maker code
CLE
tCEA
CE
WE
tAR
ALE
RE
I/O
0
~
7
tWHR
tREA
90h
00h
Address. 1cycle
ECh
Maker code
Note : For more detailed features and specifications including FAQ, please refer to Samsung Flash web site.
http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you
have any questions, please contact the SAMSUNG branch office near your office.
2
K9S5608V0B/A
K9S2808V0B/A
Revision History
Revision No History
K9S6408V0C/B
SmartMedia
TM
Draft Date
tCLS
tCLS
tCLH
tCS
Remark
CLE
CE
tCH
tCSTO
tWHR
RE
tDS
tDH
tIR
tRSTO
tRHZ
Status Output
tCHZ
tWP
WE
I/O
0
~
7
70h
tCLS
CLE
tCLS
tCLH
tCS
CE
tCH
tCEA
tWHR
RE
tDH
tDS
I/O
0
~
7
70h
tIR
tREA
tRHZ
Status Output
tCHZ
tWP
WE
0.5
1. Eliminated the duplicated AC parameter.
- AC characteristics (Before)
. Replaced t
AR1,
t
AR2
with t
AR
Parameter
ALE to RE Delay (ID read)
ALE to RE Delay (Read cycle)
CLE to RE Delay
CE Access Time
- AC characteristics (After)
Parameter
ALE to RE Delay
CLE to RE Delay
CE Access Time
Symbol
t
AR
t
CLR
t
CEA
Min
10
10
-
45
Max
-
ns
Unit
Symbol
t
AR1
t
AR2
t
CLR
t
CEA
Min
50
50
10
-
45
Max
-
-
ns
Unit
Feb. 9th 2002
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you
have any questions, please contact the SAMSUNG branch office near your office.
3
K9S5608V0B/A
K9S2808V0B/A
K9S6408V0C/B
SmartMedia
TM
SmartMedia
TM
Card
FEATURES
•Single 2.7V~3.6V Supply
•Organization
- Memory Cell Array :
8MB(K9S6408V0X) : ( 8M + 256K)bit x 8bit
16MB(K9S2808V0X) : (16M + 512K)bit x 8bit
32MB(K9S5608V0X) : (32M + 1,024K)bit x 8bit
- Data Register : (512 + 16)bit x8bit
•Automatic Program and Erase
- Page Program : (512 + 16)Byte
- Block Erase
32MB, 16MB(K9S56/2808V0X) : (16K + 512)Byte
8MB (K9S6408V0X) : (8K + 256)Byte
•528-Byte Page Read Operation
- Random Access : 10µs(Max.)
* K9S6408V0B/A : 7µs(Max.)
* K9S6408V0C : 10µs(Max.)
- Serial Page Access : 50ns(Min.)
•Fast Write Cycle Time
- Program Time : 200µs(Typ.)
- Block Erase Time : 2ms(Typ.)
•Command/Address/Data Multiplexed I/O Port
•Hardware Data Protection
- Program/Erase Lockout During Power Transitions
•Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
* K9S6408V0X : 1Million Program/Erase Cycles
- Data Retention : 10 years
•Command Register Operation
•22pad SmartMedia
TM
(SSFDC)
•Unique ID for Copyright Protection
GENERAL DESCRIPTION
Using Nand flash memory, SmartMedia provides the most cost-
effective solution for the solid state mass storage market. A pro-
gram operation is implemented by the single page of 528 bytes
in typical 200us and an erase operation is done by the single
block of 16K bytes (K9S6408V0X: 8K bytes) in typical 2ms.
Data in a page can be read out at 50ns cycle time per byte. The
I/O pins serve as ports for address and data inputs/outputs as
well as command inputs. The on-chip writing controller auto-
mates all program and erase functions including pulse repeti-
tion, where required, and internal verification and margining of
data. Even the write-intensive systems can take advantage of
the SmartMeida′s extended reliability of 100K program/erase
cycles by providing ECC(Error Correcting Code) with real time
mapping-out algorithm. (*Endurance varies according to its
density. please refer to Features). SmartMedia is an optimum
solution for data storage applications such as solid state file
storage, digital voice recorder, digital still camera and other por-
table applications requiring non-volatility.
PIN DESCRIPTION
Device
K9S2808V0X
K9S5608V0X
K9S6408V0C
K9S6408V0A/M
Unique ID Support
O
X
SmartMedia
TM
CARD(SSFDC)
PIN DESCRIPTION
Pin Name
Pin Function
Data Input/Outputs
Command Latch Enable
Address Latch Enable
Chip Enable
Read Enable
Write Enable
Write Protect
Low Voltage Detect
Ground
Ready/Busy output
Power
Ground
No Connection
22 V
CC
21 CE
20 RE
19 R/B
18 GND
17 LVD
16 I/O
7
15 I/O
6
14 I/O
5
13 I/O
4
12 V
CC
12
22
1
2
3
4
5
V
SS
CLE
ALE
WE
WP
I/O
0
I/O
1
I/O
2
I/O
3
I/O0 ~ I/O7
CLE
ALE
CE
RE
WE
WP
LVD
GND
R/B
11
1
6
7
8
9
ID 32MB
10 V
SS
11 V
SS
22 PAD SmartMedia
TM
V
CC
V
SS
N.C
NOTE
: Connect all V
CC
and V
SS
pins of each device to common power supply outputs and do not leave V
CC
or V
SS
disconnected.
The pin 17(LVD) is used to detect 5V or 3.3V product electrically. Please, refer to the SmartMedia Application note for detail.
4
K9S5608V0B/A
K9S2808V0B/A
K9S6408V0C/B
SmartMedia
TM
Figure 1. FUNCTIONAL BLOCK DIAGRAM
V
CC
V
SS
A
22
: K9S6408V0X
A
23
: K9S2808V0X
A
24
: K9S5608V0X
K9S6408V0X : 64M + 2M Bit
K9S2808V0X : 128M + 4M Bit
K9S5608V0X : 256M + 8M Bit
NAND Flash
ARRAY
K9S6408V0X : (512 + 16)Byte x 16,384
K9S2808V0X : (512 + 16)Byte x 32,768
K9S5608V0X : (512 + 16)Byte x 65,536
Page Register & S/A
A
9
- A
24
X-Buffers
Latches
& Decoders
Y-Buffers
Latches
& Decoders
A
0
- A
7
A
8
Command
Command
Register
Y-Gating
I/O Buffers & Latches
V
CC
V
SS
I/0 0
I/0 7
CE
RE
WE
Control Logic
& High Voltage
Generator
Global Buffers
Output
Driver
CLE ALE WP
5
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