To all our customers
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
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names are mentioned in the document, these names have in fact all been changed to Renesas
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corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
Cautions
Keep safety first in your circuit designs!
1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better
and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.
Notes regarding these materials
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Technology Corporation product best suited to the customer's application; they do not convey any
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circuit application examples contained in these materials.
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contained therein.
HD74HC299
8-bit Universal Shift/Storage Register (with 3-state outputs)
ADE-205-488 (Z)
1st. Edition
Sep. 2000
Description
The HD74HC299 features multiplexed inputs/outputs to achieve full 8-bit data handling in a single 20-pin
package. Due to the large output drive capability and 3-state feature, this device is ideally suited for
interfacing with bus lines in a bus oriented system. Two function select inputs and two output control
inputs are used to choose the mode of operation as listed in the function table. Synchronous parallel
loading is accomplished by taking both function select lines S
0
and S
1
high. This places the 3-state outputs
in a high impedance state, which permits data applied to the input/output lines to be clocked into the
register. Reading out of the register can be done while the outputs are enabled in any mode. A direct
overriding clear input is provided to clear the register whether the outputs are enabled or disabled.
Features
•
•
•
•
•
High Speed Operation
High Output Current: Fanout of 15 LSTTL Loads
Wide Operating Voltage: V
CC
= 2 to 6 V
Low Input Current: 1
µA
max
Low Quiescent Supply Current: I
CC
(static) = 4
µA
max (Ta = 25°C)
HD74HC299
Function Table
Inputs
Function
Select
Mode
Clear
Clear
L
L
Hold
H
H
Shift
Right
Shift
Left
Load
H
H
H
H
H
S
1
X
L
L
X
L
L
H
H
H
S
0
L
X
L
X
H
H
L
L
H
Output
Control
G
1
†
G
2
†
L
L
L
L
L
L
L
L
X
L
L
L
L
L
L
L
L
X
Serial Inputs/Outputs
Outputs
Q
H
’
L
L
Q
H0
Q
H0
Q
Gn
Q
Gn
H
L
h
Clock S
L
S
R
A/Q
A
B/Q
B
C/Q
C
D/Q
D
E/Q
E
F/Q
F
G/Q
G
H/Q
H
Q
A
’
X
X
X
L
X
X
X
X
X
X
H
L
X
X
X
X
X
H
L
X
X
X
L
L
Q
A0
Q
A0
H
L
Q
Bn
Q
Bn
a
L
L
Q
B0
Q
B0
Q
An
Q
An
Q
Cn
Q
Cn
b
L
L
Q
C0
Q
C0
Q
Bn
Q
Bn
Q
Dn
Q
Dn
c
L
L
Q
D0
Q
D0
Q
Cn
Q
Cn
Q
En
Q
En
d
L
L
Q
E0
Q
E0
Q
Dn
Q
Dn
Q
Fn
Q
Fn
e
L
L
Q
F0
Q
F0
Q
En
Q
En
Q
Gn
Q
Gn
f
L
L
Q
G0
Q
G0
Q
Fn
Q
Fn
Q
Hn
Q
Hn
g
L
L
Q
H0
Q
H0
Q
Gn
Q
Gn
H
L
h
L
L
Q
A0
Q
A0
H
L
Q
Bn
Q
Bn
a
Notes: 1. a to h; the level of steady-state input at inputs A through H, respectively. These data are
loaded into the flip-flop outputs are isolated from the input/output terminals.
2. Q
A0
to Q
H0
; the level of Q
A
through Q
H
, respectively, before the indicated steady-state input
conditions were established.
3. Q
An
to Q
Hn
; the level of Q
A
through Q
H
, respectively, before the most-recent
transition of the
clock.
4. † = ; When one or both output controls are high the eight input/output terminals are desabled to
the high-impedance state, however, sequential operation or clearing of the register is not
affected.
5. When clear is low, outputs of Q
A
’ and Q
H
’ are low, in spite of other inputs.
2
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