Preliminary Information
This document contains information on a new product. The parametric information, although not
fully characterized, is the result of testing initial devices.
M28352/M28353/M28354/M28356 (M2835x)
Dual/Triple/Quad/Hex DS3/E3/STS-1 Line Interface Unit with Integrated DJAT
The M28352/M28353/M28354/M28356 (M2835x) is a 2/3/4/6-port Line Interface Unit (LIU) and Desynchronizer/Jitter
Attenuator (DJAT) for DS3, E3, and STS-1 applications. This highly-integrated, multi-channel, low power solution is capable
of receiving data over 1800 feet of AT&T 734/728 75 ohm type cables and provide standards compliant smooth/de-jittered
clock and data to the system.
The M2835x includes diagnostics and quality monitoring functions for the detection of system and board level operating
conditions and failures. The device provides the capability to monitor RLOS and RLOS failure per GR-253, transmit loss of
signal, transmit open circuits, receiver line input opens and shorts, and clock quality and it includes a clock offset indicator.
Diagnostics capabilities include Fixed and PRBS pattern generation/detection, single error insertion and detection, bit and
error counters to support Bit Error Rate calculations, and full loopback capabilities.
Each M2835x channel can be independently configured for DS3, E3, or STS-1 applications as a LIU with desynchronizer,
LIU with jitter attenuator, or LIU with DJAT disabled or powered down. Each channel can be independently powered down
for low power operation.
Applications
Multi-service ATM switches
Optical add-drop multiplexers
Digital cross-connect systems (DACS)
DS3 to STS-1 mappers
E3 to STS-1 mappers
High-end routers
Metro-optical access switches
Distinguishing Features
Highly Integrated—Up to six independently configured LIUs with
jitter attenuator/desynchronizer channels for DS3, E3 and STS-1
applications
LIUs with Desynchronizers—For Category I interfaces, smoothes the
jitter due to the demapping, bit stuffing, and pointer adjustments in
the DS3 or E3 payloads extracted from the STS-1 frames, generating
a standards compliant clock.
LIUs with Jitter Attenuators—For Category II interfaces, the device
synchronizes to jittered DS3, E3 or STS-1 clock and data input
signals and produces a de-jittered standards compliant clock and
data output.
LIUs with Adaptive Equalization—Automatic adaptive equalization up
to 1,800 feet for AT&T 734/728 75 ohm type cables
Internally Synthesized Clocks—Three Clock Rate Adaptors (CLADs)
providing DS3, E3 and/or STS-1 clock rates from a single 19.44 MHz
crystal or external input.
(continued on page iii)
Standards Compliant—Complies with all applicable
DS3/E3/STS-1 standards:
Telcordia GR-253, GR-499
ETSI TBR-24 and ETS 300
ANSI T1.102, T1.105.03b, T1.404
ITU-T G.703, G.751, G.755, G.783, G.823, G.824, 0.151
AT&T TR54014
Functional Block Diagram
TLOSn
T A IS n
TPOSn
TNEGn
TCLKn
JAT
RPOSn
RNEGn
RCLKn
PRBS
P a tte rn
G e n /D e t
D ecoder
CDR
R e c e iv e r
R X _ L IN E P _ n
R X _ L IN E M _ n
PRBS
P a tte rn
G e n /D e t
TLOS
MON
L o g ic
M
M
M
M
O N _O P
O N _O M
O N _ IN P
O N _ IN M
Encoder
A M I/E 3
G en
&
P u ls e
Shaper
T X _ L IN E P _ n
L in e
D r iv e r
T X _ L IN E M _ n
Digital
Adaptor
Equalizer
X T A L _ IN
RLO S
XTAL_O U T
JATR X
L IU _ B Y P
ENn
L IN E R A T E 0
L IN E R A T E 1
CLADs
RESETB
IR Q B
IF _ M O D E 0
Control
IF _ M O D E 1
RWB
SCLK
OEB
S D IN
SDOUT
CSB
A D D R n /L L O O P n /R L O O P n
D A T A n /L B O n /R L O O P n
RLOSn
STS1_R EFC LK
D S3_R EFC LK
E3_R EFC LK
C L K 1 9 P 4 4 _ IO
TRST
TCLK
TMS
TDI
TDO
SCANM ODE
JTAG
.
L IU a n d J A T 0
.
.
L IU a n d J A T 1 t o 5
2835X-DSH-001-F
Mindspeed Technologies™
Preliminary Information/Mindspeed Proprietary
May 2003
Ordering Information
Model Number
M28352
M28353
M28354
M28356
Number of Channels
2
3
4
6
Package
280-ball 19 mm FPBGA
280-ball 19 mm FPBGA
280-ball 19 mm FPBGA
452-ball 27 mm PBGA
Operating Temperature
–40
°
C to 85
°
C
–40
°
C to 85
°
C
–40
°
C to 85
°
C
–40
°
C to 85
°
C
Revision History
Revision
D
E
Level
Preliminary
Date
May 2003
September 2003
Description
Changed external reference clock accuracy to +/- 20 ppm.
Added 1-second clock input pin (ONESEC_IN). Updated DJAT performance data.
Added power and current consumption. Added configuration tables for STS-1,
DS3, and E3 operation. Corrected serial interface SCLK and SDO timing parameter
description and/or values. Updated default register values. Changed name of
SECCLK_OEB bit to SECCLK_SEL and changed the description. Changed
description of TLOS_CTRL bit settings. Added CLKCTRL register for 1-second
output clock. Added register settings for selecting PRBS patterns. Updated notes
on how to read counters. Added DJAT control register settings.
Decreased the duration of parallel interface CSB inactive (i.e, timing parameters Tpwh
& Tprh).
F
October 2003
Corrected the following: register partitioning tables; Revision E history description;
TPOS/TNEG pin description; ONESEC_IN pin type; note under the SECCLK_SEL bit
in SECTIMCTRL register (address 0x00A); description of PROG_EN_FM bit in the
JATCTRL register (address 0x15B). Edited descriptions of the following: RPOS/
RNEG pin; ONESEC_IN pin; CLAD section 2.2.3.2; RLOS bit in CH_LST2 register
(address 0xn12); RLOS_INT bit in CH_INTST2 register (address 0xn16);
RXPRBS_CTRL2 register (address 0xn20); RXPRBS_CTRL3 register (address
0xn21); TXPRBS_CTRL2 register (address 0xn42); TXPRBS_CTRL3 register
address 0xn43); LOSF_MODE bit in the RLOS_CTRL register (address 0xn56).
© 2003, Mindspeed TechnologiesTM, Inc. All rights reserved.
Information in this document is provided in connection with Mindspeed TechnologiesTM ("MindspeedTM") products. These materials are
provided by Mindspeed as a service to its customers and may be used for informational purposes only. Except as provided in Mindspeed’s
Terms and Conditions of Sale for such products or in any separate agreement related to this document, Mindspeed assumes no liability
whatsoever. Mindspeed assumes no responsibility for errors or omissions in these materials. Mindspeed may make changes to specifications
and product descriptions at any time, without notice. Mindspeed makes no commitment to update the information and shall have no
responsibility whatsoever for conflicts or incompatibilities arising from future changes to its specifications and product descriptions. No license,
express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
THESE MATERIALS ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, RELATING TO SALE
AND/OR USE OF MINDSPEED PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR
PURPOSE, CONSEQUENTIAL OR INCIDENTAL DAMAGES, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR
OTHER INTELLECTUAL PROPERTY RIGHT. MINDSPEED FURTHER DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF
THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. MINDSPEED SHALL NOT BE
LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST
REVENUES OR LOST PROFITS, WHICH MAY RESULT FROM THE USE OF THESE MATERIALS.
Mindspeed products are not intended for use in medical, lifesaving or life sustaining applications. Mindspeed customers using or selling
Mindspeed products for use in such applications do so at their own risk and agree to fully indemnify Mindspeed for any damages resulting from
such improper use or sale.
2835X-DSH-001-F
Mindspeed Technologies™
Preliminary Information/Mindspeed Proprietary
ii
M28352/M28353/M28354/M28356 (M2835x) Data Sheet
Distinguishing Features
(continued from front page)
Operating Conditions
Uses 3.3 V and 1.8 V supplies
Operates from –40° C to 85° C
Three Interfaces for Configuration:
Hardware interface pins
Serial microprocessor interface port
Parallel microprocessor interface
port
Qualify Monitoring
Determines the integrity of the
signals
Continuously monitor the quality of
the connections
RLOS receive loss of signal indicator
circuit compliant with
ITU-T G.775
TLOS internal or external transmit
loss of signal indication
DC continuity check of receive input
ITU-T G.772-compliant
monitoring
circuit that monitors the performance
of transmit signals
Clock meter indicates the quality of
recovered receive clocks used to alert
network operators of variations in the
network
Alarm Indication Signal—TAIS alarm
indication signal for DS3 AIS and E3 AIS
Suppression Encoding Error Counters
Line Code Violation (LCV) Counter
Bipolar Violation (BPV) Counter
Excessive Zeros (EXZ) Counter
Event Latching—One-second timer for
event latching of counters
Diagnostics, Per Channel:
PRBS detection and/or generation
3-bit Fixed Pattern detection and/or
generation (B3ZS testing)
4-bit Fixed Pattern detection and/or
generation (HDB3 testing)
Single error insertion into generated
pattern
Single bit error detection and
counting
Received bit counting to support Bit
Error Rate calculations
Loopbacks, Per Channel:
Line loopback
Analog loopback (analog line receive
data looped back to analog transmit
data)
Source loopback
JTAG Interface—JTAG (IEEE 1149.1)
boundary scan
Seamless Framer Interface —Interfaces
seamlessly with other components in
Mindspeed's DS3/E3 family of devices
such as CX28365 and CX2834x
(multiport) DS3/E3 framers.
Power Consumption
Independent channel power-down
control for low power operation
Size
6-port device in a 27 mm PBGA package
2, 3, and 4-port devices in a 19 mm
FPBGA package
2835X-DSH-001-F
Mindspeed Technologies™
Preliminary Information/Mindspeed Proprietary
iii
M28352/M28353/M28354/M28356 (M2835x) Data Sheet
iv
Mindspeed Technologies™
Preliminary Information/Mindspeed Proprietary
2835X-DSH-001-F
Contents
Contents
Figures
Tables
1.1
1.2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .v
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Pin Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2.1
M28356 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2.2
M28354 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.2.3
M28353 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.2.4
M28352 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.0 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.3
2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1
2.2
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Clock Rate Adaptor – CLAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.2.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.2.2
Crystal Oscillator Circuitry Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.2.2.1
Crystal Oscillator Circuitry Not Bypassed and the CLADs Enabled . . . . . . . . . . . . 2-4
2.2.2.2
Crystal Oscillator Circuitry Not Bypassed and the CLADs Disabled . . . . . . . . . . . 2-5
2.2.3
Crystal Oscillator Circuitry Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.2.3.1
Crystal Oscillator Circuitry Bypassed and the CLADs Enabled . . . . . . . . . . . . . . . 2-6
2.2.3.2
Crystal Oscillator Circuitry Bypassed and the CLADs Disabled. . . . . . . . . . . . . . . 2-7
Line Interface Unit – LIU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.3.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.3.2
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.3.2.1
AMI/B3ZS/HBD3 Encoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.3.2.2
Pulse Shaper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.3.2.3
Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.3.2.4
Transmit Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.3.2.5
Alarm Indication Signal Generator – AIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.3.3
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.3.3.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.3.3.2
AGC/VGA Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.3.3.3
Receive Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.3.3.4
PLL Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.3.3.5
Loss of Signal Detector – RLOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.3.3.6
Data Squelching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2.3.3.7
AMI/B3ZS/HDB3 Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2.3.3.8
Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
2.3.3.9
DC Continuity Check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
Jitter Attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
2.3
2.4
2835X-DSH-001-F
Mindspeed Technologies™
Preliminary Information/Mindspeed Proprietary
April 2003
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EEWORLD
