MIC2593
Dual-Slot PCI Hot Plug Controller
General Description
The MIC2593 is a power controller supporting power
distribution requirements for Peripheral Component
Interconnect hot plug systems compliant to PCI v2.3 and
PCI-X 1.0b. TheMIC2593 provides complete power control
support for two PCI slots, including the 3.3V
AUX
defined by
the PCI v2.3 specification. Support for +5V, +3.3V, +12V,
and –12V supplies is provided and includes programmable
current limit, voltage supervision, fault reporting, and circuit
breaker functions which provide fault isolation. The
MIC2593 also incorporates an SMBus interface that
provides complete status and control of power within each
slot.
Data sheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
Features
•
Supports two completely independent PCI slots:
– Compliant to PCI v2.3 and PCI-X 1.0b power
control requirements
– Provides all major power control functions for two
independent PCI-X 2.0 slots
•
Five voltage supplies supported: +12V, -12V,
+5V,+3.3V, and +3.3V
AUX
– Integrated gate driver circuits, current sense, and
power MOSFETs for 3.3V
AUX
, +12V, and –12V
– High-side +5V and +3.3V gate driver circuits for
external N-Channel MOSFETs
•
Overcurrent protection with adjustable timeout
eliminates false tripping of circuit breakers
•
Dual-level, dual-speed overcurrent detection circuitry
for quick fault response without nuisance tripping
•
Slot power control with “Power-is-Good” and Fault
status reporting
– Via software over an SMBus interface or
– Via dedicated hardware input/output lines: Hot
Plug Interface (HPI)
•
Complete thermal isolation between circuitry for Slot A
and Slot B
•
One General Purpose Input (GPI) pin per slot for
mechanical switch or plug-in card retention/removal
input
Applications
•
PCI hot plug power distribution
Ideal Applications:
•
Mid- and High-end Server Applications compliant to PCI
v2.3, PCI-X 1.0b, and PCI-X 2.0
___________________________________________________________________________________________________________
Ordering Information
Part Number
MIC2593-2BTQ
MIC2593-2YTQ
Note:
Contact factory for availability of the MIC2593-5YTQ option that disables the 100mV fast-trip threshold.
LITTLE FOOT is a registered trademark of Siliconix Incorporated.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (
408
) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
5V & 3V Fast-trip
Threshold
100mV
100mV
+12V & –12V Fast-trip
Threshold
1.5A/0.4A
1.5A/0.4A
Operating
Temp. Range
0° to +70°C
0° to +70°C
Package
48-Pin TQFP
48-Pin TQFP
Lead Finish
Standard
Pb-Free
September 2008
M9999-092208
Micrel, Inc.
MIC2593
Typical Application
Power
Supply
+12V
12V
+5.0V
+3.3V
0.1µF
0.1µF
VSTBY
0.1µF
5
32
17
18
0.1µF
PCI Connector
12VINA 12VINB
VSTBYA
12MVINA 12MVINB
VAUXA
5VINA
15
PCI Bus
0.1µF
11
6
0.1µF
26
VSTBYB
5VSENSEA
7
R
SENSE
*R
12VGATEA
3.3VAUXA
375mA
3
34
12VSLEWA
12VSLEWB
5VGATEA
5VOUTA
3VINA
8
0.01µF
9
Si4420DY
**C3
**C4
12
0.1µF
13
R
SENSE
2
35
CFILTERA
CFILTERB
3VSENSEA
3VGATEA
*R
3VGATEA
V
STBY
**C1
**C2
14
16
10
19
Si4420DY
3.3V, 7.6A
12V, 0.5A
–12V, 0.1A
100k
GPIA
GPIB
100k
4
38
GPIA
GPIB
MIC2593
3VOUTA
12VOUTA
12MVOUTA
V
STBY
C
GATE
0.01µF
31
5VINB
10k × 4
AUXENA
AUXENB
ONA
ONB
Hot Plug
Controller
V
STBY
45
42
44
43
0.1µF
30
5VSENSEB
AUXENA
AUXENB
ONA
ONB
R
SENSE
*R
12VGATEB
5VGATEB
5VOUTB
29
0.01µF
28
Si4420DY
5V, 5A
0.1µF
10k × 2
/FAULTA
/FAULTB
1
36
3VINB
/FAULTA
/FAULTB
A0
A1
A2
/INT
SCL
SDA
3VSENSEB
3VGATEB
3VOUTB
12VOUTB
12MVOUTB
VAUXB
GND
GND
R
SENSE
25
24
*R
3VGATEB
23
21
27
20
22
33
46
Si4420DY
3.3V, 7.6A
12V, 0.5A
–12V, 0.1A
3.3VAUXB
41
SMBus
Base
Address
V
STBY
40
39
37
47
48
C
GATE
0.01µF
10k × 3
SDA
SMBus I/O
SCL
/INT
*
PCI Bus
SDA
SCL
/INT
Management
Controller
PCI Connector
Values for R
5VGATE[A/B]
and R
3VGATE[A/B]
may vary depending upon the C
GS
of the external MOSFETs.
** Values determined by design requirements. See “Functional Description” section for detailed information.
# MBRS140T3 or equivalent is recommended.
Bold lines indicate high current paths
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MIC2593
Pin Configuration
Hot-Plug
Control
Interface
SDA
SCL
GND
AUXENA
ONA
ONB
AUXENB
A0
A1
A2
GPIB
/INT
/FAULTA
CFILTERA
12VSLEW
GPI
12VINA
5VINA
5VSENSEA
5VGATEA
5VOUTA
12VOUTA
VSTBYA
3VINA
/FAULTB
CFILTERB
12VSLEWB
GND
12VINB
5VINB
5VSENSEB
5VGATEB
5VOUTB
12VOUTB
VSTBYB
3VINB
Slot A
Interface
3VSENSEA
3VGATEA
VAUXA
3VOUTA
12MVINA
12MVINB
12MVOUTA
12MVOUTB
3VOUTB
VAUXB
3VGATEB
3VSENSEB
Slot B
Interface
48-Pin TQFP (TQ)
Pin Description
Pin Number
5, 32
Pin Name
12VINA, 12VINB
Pin Function
+12V Supply Power [A/B]: Pin 5 is the input to the drain side of the internal
MOSFET switch for +12V Slot A. Pin 32 is the input to the drain side of the
internal MOSFET switch for +12V Slot B. These two pins must ultimately
connect to each other within 10cm of the MIC2593. An undervoltage lockout
circuit (UVLO) prevents the switches from turning on while this input is less than
its lockout threshold.
+12V Output [A/B]: Pin 10 is connected to the source terminal of the internal
MOSFET switch for +12V Slot A and pin 27 is connected similarly for Slot B.
–12V Supply Power [A/B]: Pin 17 is the input to the drain side of the internal
MOSFET switch for +12V Slot A. Pin 18 is the input to the drain side of the
internal MOSFET switch for –12V Slot B. These two pins must ultimately
connect to each other within 10cm of the MIC2593. An undervoltage lockout
circuit (UVLO) prevents the switches from turning on while this input is less than
its lockout threshold.
–12V Output [A/B]: Pin 19 is connected to the source terminal of the internal
MOSFET switch for –12V Slot A and pin 20 is connected similarly for Slot B.
12V Slew Rate Control [A/B]: Connect capacitors between these pins and
ground to set the output slew rates of the +12V and –12V supplies. See the
“Functional Description” section for more details.
10, 27
17, 18
12VOUTA, 12VOUTB
12MVINA, 12MVINB
19, 20
3, 34
12MVOUTA, 12MVOUTB
12VSLEWA, 12VSLEWB
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Pin Number
6, 31
Pin Name
5VINA, 5VINB
Pin Function
MIC2593
5V Supply Power and Sense Input [A/B]: Pin 6 is the (+) Kelvin-sense
connection to the supply side of the sense resistor for 5V Slot A. Pin 31 is the
(+) Kelvin sense connection to the supply side of the sense resistor for 5V Slot
B. These two pins must ultimately connect to each other within10cm of the
MIC2593. An undervoltage lockout circuit (UVLO) prevents the switches from
turning on while this input is less than its lockout threshold.
5V Circuit Breaker Sense Input [A/B]: The current limit thresholds are set by
connecting sense resistors between these pins and 5VIN[A/B]. When the
current limit threshold of IR = 50mV is reached, the 5VGATE[A/B] pin is
modulated to maintain a constant voltage across the sense resistor and
therefore a constant current into the load. If the 50mV threshold is exceeded for
t
FLT
(see CFILTER[A/B] pin description), the circuit breaker is tripped and the
GATE pin for the affected supply’s external MOSFET is immediately pulled low.
5V Power-Good Sense Inputs: Connect to 5V[A/B] outputs. Used to monitor the
5V output voltages for Power-is-Good status.
5V Gate Drive Output [A/B]: Each pin connects to the gate of an external N-
Channel MOSFET. During power-up, the C
GATE
and the C
GS
of the MOSFETs
are charged by a 25µA current source. This controls the value of dv/dt seen at
the source of the MOSFETs, and hence the current flowing into the load
capacitance.
During current-limit events, the voltage at the pin is adjusted to maintain constant
current through the switch for a period of t
FLT
. Whenever an overcurrent, thermal
shutdown, or input undervoltage fault condition occurs, the GATE pin for the
affected slot is immediately brought low.
During power-down, these pins are discharged by an internal current source.
7, 30
5VSENSEA, 5VSENSEB
9, 28
8, 29
5VOUTA, 5VOUTB
5VGATEA, 5VGATEB
12, 25
3VINA, 3VINB
3.3V Supply Power and Sense Input [A/B]: Pin 12 is the (+) Kelvin-sense
connection to the supply side of the sense resistor for 3.3V Slot A. Pin 25 is the
(+) Kelvin-sense connection to the supply side of the sense resistor for 3.3V Slot
B. These two pins must ultimately connect to each other within 10cm of the
MIC2593. An undervoltage lockout circuit (UVLO) prevents the switches from
turning on while this input is less than its lockout threshold.
3V Circuit Breaker Sense Input [A/B]: The current limit thresholds are set by
connecting sense resistors between these pins and 3VIN[A/B]. When the
current limit threshold of IR = 50mV is reached, the 3VGATE[A/B] pin is
modulated to maintain a constant voltage across the sense resistor and
therefore a constant current into the load. If the 50mV threshold is exceeded for
t
FLT
(see CFILTER[A/B] pin description), the circuit breaker is tripped and the
GATE pin for the affected supply’s external MOSFET is immediately pulled low.
3.3V Power-Good Sense Inputs: Connect to 3.3V[A/B] outputs. Used to monitor
the 3.3V output voltages for Power-is-Good status.
3V Gate Drive Output [A/B]: Each pin connects to the gate of an external N-
channel MOSFET. During power-up, the C
GATE
and the C
GS
of the MOSFETs
are connected to a 25µA current source. This controls the value of dv/dt seen at
the source of the MOSFETs, and hence the current flowing into the load
capacitance.
During current limit events, the voltage at this pin is adjusted to maintain
constant current through the switch for a period of t
FLT
. Whenever an
overcurrent, thermal shutdown, or input undervoltage fault condition occurs, the
GATE pin for the affected slot is immediately brought low. During power down,
these pins are discharged by an internal current source.
13, 24
3VSENSEA, 3VSENSEB
16, 21
14, 23
3VOUTA, 3VOUTB
3VGATEA, 3VGATEB
11, 26
VSTBYA, VSTBYB
.3V Standby Input Voltage: Required to support PCI VAUX output. Additionally,
the SMBus logic and internal registers run off of VSTBY[A/B] to ensure that the
MIC2593 is accessible during standby modes. A UVLO circuit prevents turn-on
of this supply until VSTBY[A/B] rises above its UVLO threshold. Both pins must
be connected together externally at the IC.
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Pin Number
15, 22
Pin Name
VAUXA, VAUXB
Pin Function
MIC2593
3.3VAUX[A/B] Output to PCI Card Slot: These outputs connect the 3.3AUX pin
of the PCI connectors to VSTBY[A/B] via internal 400mΩ MOSFETs. These
outputs are current limited and protected against short-circuit faults.
Enable Inputs: Rising-edge triggered. Used to enable or disable the MAINA and
MAINB (5V, 3.3V, +12V and –12V) outputs. Taking ON[A/B] low after a fault
resets the 5V, 3.3V, +12V and/or –12V fault latches for the affected slot. Tie
these pins to GND if using SMI power control. Also, see pin description for
/FAULTA and /FAULTB.
Enable Inputs: Rising-edge triggered. Used to enable or disable VAUXA and
VAUXB outputs. Taking AUXEN[A/B] low after a fault resets the respective slot’s
Aux Output Fault Latch. Tie these pins to GND if using SMI power control. Also,
see pin description for /FAULTA and /FAULTB.
Overcurrent Timer (Filter) Capacitor [A/B]: Capacitors connected between these
pins and GND set the duration of t
FLT
. t
FLT
is the amount of time for which a slot
remains in current limit before its circuit breaker is tripped.
/FAULT[A/B] Outputs: Open-drain, active-low. Asserted whenever the circuit
breaker trips due to a fault condition (overcurrent, input undervoltage,
overtemperature). Each pin requires an external pull-up resistor to VSTBY.
Bringing the slot’s ON[A/B] pin low resets /FAULT[A/B] if /FAULT[A/B] was
asserted in response to a fault condition on one of the slot’s MAIN outputs (5V,
3.3V, +12V, or –12V).
/FAULT[A/B] is reset by bringing the slot’s AUXEN[A/B] pin low if /FAULT[A/B]
was asserted in response to a fault condition on the slot’s VAUX output. If a fault
condition occurred on both the MAIN and VAUX[A/B] outputs of the same slot,
then both ON[A/B] and AUXEN[A/B] must be brought low to de-assert the
/FAULT[A/B] output.
44, 43
ONA, ONB
45, 42
AUXENA, AUXENB
2, 35
CFILTERA, CFILTERB
1, 36
/FAULTA, /FAULTB
4, 38
40, 41
GPIA, GPIB
A1, A0
General Purpose Inputs: The states of these two inputs are available by reading
the Common Status Register, Bits [4:5]. If not used, connect each pin to GND.
SMBus Address Select Pins: Connect to ground or leave open in order to 41 A0
program device SMBus base address. These inputs have internal pull-up
resistors to VSTBY[A/B].
SMBus Data: Bidirectional SMBus data line.
SMBus Clock: Input.
Interrupt Output: Open-drain, active-low. Asserted whenever a power fault is
detected if the INTMSK bit (CS Register Bit D[3]) is a logical "0". This output is
de-asserted by performing an "echo reset" to the appropriate fault bit(s) in the
STAT[A/B] and/or CS registers. This pin requires an external pull-up resistor to
V
STBY
.
IC Ground Connections: Tie directly to the system’s analog ground plane
directly at the device.
48
47
37
SDA
SCL
/INT
33, 46
GND
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