®
X9530
Data Sheet
March 10, 2005
FN8211.0
Temperature Compensated Laser Diode
Controller
FEATURES
• Compatible with Popular Fiber Optic Module
Specifications such as Xenpak, SFF, SFP, and
GBIC
• Package
—14 Pin TSSOP
—15 Lead 2.7 x 3.5mm CSP (Chip-Scale
Package)
• Two Programmable Current Generators
—±1.6 mA max.
—8-bit (256 Step) Resolution
• Integrated 6 bit A/D Converter
• Temperature Compensation
—Internal or External Sensor
—-40°C to +100°C Range
—2.2°C/step resolution
—EEPROM Look-up Tables
• Hot Pluggable
• 2176-bit EEPROM
—17 Pages
—16 Bytes per Page
• Write Protection Circuitry
—Intersil BlockLock™
—Logic Controlled Protection
—2-wire Bus with 3 Slave Address Bits
• 3V to 5.5V, Single Supply Operation
LASER DIODE BIAS CONTROL APPLICATIONS
• SONET and SDH Transmission Systems
• 1G and 10G Ethernet, and Fibre Channel Laser
Diode Driver Circuits
TYPICAL APPLICATION
DESCRIPTION
The X9530 is a highly integrated laser diode bias
controller which incorporates two digitally controlled
Programmable Current Generators, temperature
compensation with dedicated look-up tables, and
supplementary EEPROM array. All functions of the
device are controlled via a 2-wire digital serial
interface.
Two temperature compensated Programmable
Current Generators, vary the output current with
temperature according to the contents of the
associated nonvolatile look-up table. The look-up table
may be programmed with arbitrary data by the user,
via the 2-wire serial port, and either an internal or
external temperature sensor may be used to control
the output current response. These temperature
compensated pro-grammable currents maybe used to
control the modulation current and the bias current of
a laser diode.
The integrated General Purpose EEPROM is included
for product data storage and can be used for
transceiver module information storage in laser diode
applications.
GBIC / SFP / XFP Module
V
CC
High Speed
Data Input
Laser
Diode
Driver
Circuit
LD
MPD
X9530
I
1
MOD_DEF
(0)
MOD_DEF
(1)
SDA
SCK
I
2
I
PINSET
/I
BIASSET
I
MODSET
I
LD
I
MON
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9530
BLOCK DIAGRAM
Voltage
Reference
VRef
VSense
ADC
Mux
Temperature
Sensor
Look-up
Table 1
Control
& Status
General
Purpose
Memory
Mux
DAC 1
I1
R1
Mux
Look-up
Table 2
Mux
DAC 2
R2
I2
SDA
SCL
WP
A2, A1, A0
2-Wire
Interface
PIN CONFIGURATION
3
A0
A1
A2
Vcc
WP
SCL
SDA
1
2
3
4
5
6
7
14
13
12
11
10
9
8
I2
VRef
VSense
Vss
R2
R1
I1
A
B
C
D
E
A0
Vcc
SCL
2
I2
1
VRef
A1 VSense
A2
Vss
R2
R1
SDA Vss
WP
I1
TSSOP 14L
DEVICE DESCRIPTION
The X9530 combines two Programmable Current
Generators, and integrated EEPROM with Block
Lock™
protection,
in
one
package.
The
Programmable Current Generators are ideal for use in
fiber optic Modulation Current require temperature
control. The combination of the X9530 functionality
and Intersil’s Chip-Scale package lowers system cost,
increases reliability, and reduces board space
requirements.
Two on-chip Programmable Current Generators may
be independently programmed to either sink or source
current. The maximum current generated is
determined by using an externally connected
programming resistor, or by selecting one of three
predefined values. Both current generators have a
maximum output of ±1.6 mA, and may be controlled to
an absolute resolution of 0.39% (256 steps / 8 bit).
Both current generators may be driven using an on-
board temperature sensor, an external sensor, or
Control Registers. The internal temperature sensor
2
Top View - Bumps Down CSP – B15
operates over a very broad temperature range (-40
°
C
to +100
°
C). The sensor output (internal or external)
drives a 6-bit A/D converter, whose output selects one
of 64 bytes from each nonvolatile look-up table (LUT).
The contents of the selected LUT row (8-bit wide)
drives the input of an 8-bit D/A converter, which
generates the output current.
All control and setup parameters of the X9530,
including the look-up tables, are programmable via the
2-wire serial port.
The general purpose memory portion of the device is a
CMOS serial EEPROM array with Intersil’s Block
Lock
TM
protection. This memory may be used to store
fiber optic module manufacturing data, serial numbers,
or various other system parameters.
The EEPROM array is internally organized as 272 x 8
bits with 16-Byte pages, and utilizes Intersil’s
proprietary Direct Write™ cells, providing a minimum
endurance of 100,000 Page Write cycles and a
minimum data retention of 100 years.
FN8211.0
March 10, 2005
X9530
PIN ASSIGNMENTS
TSSOP
Pin
1
CSP
Pin
A3
Pin
Name
A0
Pin Description
Device Address Select Pin 0.
This pin determines the LSB of the device address
required to communicate using the 2-wire interface. The A0 pin has an on-chip pull-
down resistor.
Device Address Select Pin 1.
This pin determines the intermediate bit of the device
address required to communicate using the 2-wire interface. The A1 pin has an on-chip
pull-down resistor.
Device Address Select Pin 2.
This pin determines the MSB of the device address re-
quired to communicate using the 2-wire interface. The A2 pin has an on-chip pull-down
resistor.
Supply Voltage.
Write Protect Control Pin.
This pin is a CMOS compatible input. When LOW, Write
Protection is enabled preventing any “Write” operation. When HIGH, various areas of
the memory can be protected using the Block Lock bits BL1 and BL0. The WP pin has
an on-chip pull-down resistor, which enables the Write Protection when this pin is left
floating.
Serial Clock.
This is a TTL compatible input pin. This input is the 2-wire interface clock
controlling data input and output at the SDA pin.
Serial Data.
This pin is the 2-wire interface data into or out of the device. It is TTL
compatible when used as an input, and it is Open Drain when used as an output. This
pin requires an external pull up resistor.
Current Generator 1 Output.
This pin sinks or sources current. The magnitude and di-
rection of the current is fully programmable and adaptive. The resolution is 8 bits.
Current Programming Resistor 1.
A resistor between this pin and Vss can set the
maximum output current available at pin I1. If no resistor is used, the maximum current
must be selected using control register bits.
Current Programming Resistor 2.
A resistor between this pin and Vss can set the
maximum output current available at pin I2. If no resistor is used, the maximum current
must be selected using control register bits.
Ground.
Sensor Voltage Input.
This voltage input may be used to drive the input of the on-chip
A/D converter.
Reference Voltage Input or Output.
This pin can be configured as either an Input or
an Output. As an Input, the voltage at this pin is provided by an external source. As an
Output, the voltage at this pin is a buffered output voltage of the on-chip bandgap refer-
ence circuit. In both cases, the voltage at this pin is the reference for the A/D
converter and the two D/A converters.
Current Generator 2 Output.
This pin sinks or sources current. The magnitude and di-
rection of the current is fully programmable and adaptive. The resolution is 8 bits.
2
B2
A1
3
C2
A2
4
5
B3
E3
Vcc
WP
6
7
C3
D3
SCL
SDA
8
9
E2
E1
I1
R1
10
D1
R2
11
12
13
C1, D2
B1
A1
Vss
VSense
VRef
14
A2
I2
3
FN8211.0
March 10, 2005
X9530
PRINCIPLES OF OPERATION
CONTROL AND STATUS REGISTERS
The Control and Status Registers provide the user
with a mechanism for changing and reading the value
of various parameters of the X9530. The X9530
contains seven Control, one Status, and several
Reserved registers, each being one Byte wide (See
Figure 1). The Control registers 0 through 6 are
located at memory addresses 80h through 86h
respectively. The Status register is at memory address
87h, and the Reserved registers at memory address
88h through 8Fh.
All bits in Control register 6 always power-up to the
logic state “0”. All bits in Control registers 0 through 5
power-up to the logic state value kept in their
corresponding nonvolatile memory cells. The
nonvolatile bits of a register retain their stored values
even when the X9530 is powered down, then powered
back up. The nonvolatile bits in Control 0 through
Control 5 registers are all preprogrammed to the logic
state “0” at the factory.
Bits indicated as “Reserved” are ignored when read,
and must be written as “0”, if any Write operation is
performed to their registers.
A detailed description of the function of each of the
Control and Status register bits follows:
Control Register 0
This register is accessed by performing a Read or
Write operation to address 80h of memory.
BL1, BL0: B
LOCK
L
OCK PROTECTION BITS
(N
ON
-
VOLATILE
)
These two bits are used to inhibit any write operation
to certain addresses within the memory array. The
protected region of memory is determined by the
values of the two bits as shown in the table below:
Protected Addresses
(Size)
None (Default)
00h to 7Fh (128 bytes)
00h to 7Fh and 90h to
CFh (192 bytes)
00h to 7Fh and 90h to
10Fh (256 bytes)
Notice that if the Write Protect (WP) input pin of the
X9530 is active (LOW), then any write operation to
the memory is inhibited, irrespective of the Block
Lock bit settings.
VRM: V
OLTAGE
R
EFERENCE PIN
M
ODE
(N
ON
-
VOLATILE
)
The VRM bit configures the Voltage Reference pin
(VRef) as either an input or an output. When the VRM
bit is set to “0” (default), the voltage at pin VRef is an
output from the X9530’s internal voltage reference.
When the VRM bit is set to “1”, the voltage reference
for the VRef pin is external. See Figure 2.
ADCIN: A/D C
ONVERTER
I
NPUT
S
ELECT
(N
ON
-
VOLATILE
)
The ADCIN bit selects the input of the on-chip A/D
converter. When the ADCIN bit is set to “0” (default),
the output of the on-chip temperature sensor is the
input to the A/D converter. When the ADCIN bit is set
to “1”, the input to the A/D converter is the voltage at
the VSense pin. See Figure 4.
ADC
FILT
O
FF
: ADC F
ILTERING
C
ONTROL
(N
ON
-
VOLATILE
)
When this bit is “1”, the status register at 87h is
updated after every conversion of the ADC. When this
bit is “0” (default), the status register is updated after
four consecutive conversions with the same result.
NV1234: C
ONTROL REGISTERS
1, 2, 3,
AND
4
VOLA
-
TILITY MODE SELECTION BIT
(N
ON
-
VOLATILE
)
When the NV1234 bit is set to “0” (default), bytes
written to Control registers 1, 2, 3, and 4 are stored in
volatile cells, and their content is lost when the X9530
is powered down. When the NV1234 bit is set to “1”,
bytes written to Control registers 1, 2, 3, and 4 are
stored in both volatile and nonvolatile cells, and their
value doesn’t change when the X9530 is powered
down and powered back up. See “Writing to Control
Registers” on page 17.
I1DS: C
URRENT
G
ENERATOR
1 D
IRECTION
S
ELECT
B
IT
(N
ON
-
VOLATILE
)
The I1DS bit sets the polarity of Current Generator 1,
DAC1. When this bit is set to “0” (default), the Current
Generator 1 of the X9530 is configured as a Current
Source. Current Generator 1 is configured as a
Current Sink when the I1DS bit is set to “1”. See
Figure 5.
Partition of array
locked
None (Default)
BL1
0
0
1
1
BL0
0
1
0
1
GPM
GPM, LUT1
GPM, LUT1, LUT2
If the user attempts to perform a write operation to a
protected region of memory, the operation is aborted
without changing any data in the array.
4
FN8211.0
March 10, 2005
X9530
Figure 1. Control and Status Register Format
Byte
Address
MSB
7
80h
Non-Volatile
6
5
4
3
2
1
LSB
0
Register
Name
I2DS
I1DS
NV1234
Control
1, 2, 3, 4
Volatility
0: Volatile
1: Non-
volatile
ADCfiltOff
ADC
filtering
0: On
1: Off
ADCIN
ADC Input
0: Internal
1: External
VRM
Voltage
Reference
Mode
0: Internal
1: External
BL1
BL0
Control 0
I1 and I2 Direction
0: Source
1: Sink
Block Lock
00: None Locked
01: GPM Locked
10: GPM, LUT1, Locked
11: GPM, LUT1, LUT2
Locked
Direct Access to LUT1
81h
Volatile or
Non-Volatile
Reserved
Reserved
L1DA5
L1DA4
L1DA3
L1DA2
L1DA1
L1DA0
Control 1
Direct Access to LUT2
82h
Volatile or
Non-Volatile
Reserved
Reserved
L2DA5
L2DA4
L2DA3
L2DA2
L2DA1
L2DA0
Control 2
Direct Access to DAC1
83h
Volatile or
Non-Volatile
D1DA7
D1DA6
D1DA5
D1DA4
D1DA3
D1DA2
D1DA1
D1DA0
Control 3
Direct Access to DAC2
84h
Volatile or
Non-Volatile
D2DA7
D2DA6
D2DA5
D2DA4
D2DA3
D2DA2
D2DA1
D2DA0
Control 4
85h
Non-Volatile
D2DAS
Direct
Access
to DAC2
0: Disabled
1: Enabled
L2DAS
Direct
Access
to LUT2
0: Disabled
1: Enabled
D1DAS
Direct
Access
to DAC1
0: Disabled
1: Enabled
L1DAS
Direct
Access
to LUT1
0: Disabled
1: Enabled
I2FSO1
I2FSO0
I1FSO1
I1FSO0
Control 5
R2 Selection
00: External
01: Low Internal
10: Middle Internal
11: High Internal
R1 Selection
00: External
01: Low Internal
10: Middle Internal
11: High Internal
86h
Volatile
WEL
Write
Enable
Latch
0: Write
Disabled
1: Write
Enabled
Reserved
Reserved Reserved
Reserved
Reserved
Reserved
Reserved
Control 6
ADC Output
87h
Volatile
AD5
AD4
AD3
AD2
AD1
AD0
Reserved
Reserved
Status
Registers in byte addresses 88h through 8Fh are reserved.
5
FN8211.0
March 10, 2005
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