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FN8203
Rev 2.00
October 17, 2005
X9460
Low Noise, Low Cost, High End Features, Dual Audio Log Potentiometer Dual
Audio Control Digitally Controlled Potentiometer (XDCP™)
The X9460 integrates two digitally controlled potentiometer
(XDCP) on a monolithic CMOS integrated circuit. The two
XDCPs can be used as stereo gain controls in audio
applications. Read/Write operations can directly access
each channel independently or both channels
simultaneously. Increment/Decrement can adjust each
channel independently or both channels simultaneously.
The X9460 contains a zero amplitude wiper switching circuit
that delays wiper changes until the next zero crossing of the
audio signal.
The digitally controlled potentiometer is implemented using
31 polysilicon resistors in a log array. Between each of the
resistors are tap points connected to the wiper terminal
through switches. The XDCPs are designed to minimize
wiper noise to avoid pops and clicks during audio volume
transitions. The position of the wiper on the array is
controlled by the user through the 2-wire serial bus interface.
Power-up reset the wiper to the mute position.
Features
• Dual Audio Control – Two 32 Taps Log Pots
• Zero Amplitude Wiper Switching
• 2-Wire Serial Interface
4 Slave Byte Addresses for Writes[A1,A0]
• Total Resistance: 33k Each XDCP (Typical)
• Dual Voltage Operation
V+/V- = ±2.7 to ±5.5V
• Temp Range = -40°C to +85°C
• Package Options
14 L d TSSOP
• Zero Amplitude Wiper Switching
• Pb-Free Plus Anneal Available (RoHS Compliant)
Audio Performance
• 0 to - 62dB Volume Control
• -92dB Mute
- Power-Up to Mute Position
• SNR -96dB
• THD+N: -95dB @1kHz
Pinout
X9460
(14 LD TSSOP)
TOP VIEW
SDA
SCL
V
CC
V+
V
SS
A0
A1
1
2
3
4
5
6
7
X9460
14
13
12
11
10
9
8
V-
R
H-right
R
L-right
R
W-right
R
H-left
R
L-left
R
W-left
• Crosstalk Rejection: -102dB @ 1kHz
• Channel-to-Channel Variation: ± 0.1dB
• 3dB-Cutoff: 100kHz
Applications
• Set Top Boxes
• Stereo Amplifiers
• DVD Players
• Portable Audio Products
Ordering Information
PART NUMBER
X9460KV14I*
X9460KV14IZ* (Note)
X9460KV14I-2.7*
X9460KV14IZ-2.7* (Note)
PART MARKING
X9460KV I
X9460KV Z I
X9460KV G
X9460KV Z G
2.7 to 5.5
V
CC
LIMITS (V)
5V ± 10%
TEMP RANGE (°C)
-40 to +85
-40 to +85
-40 to +85
-40 to +85
PACKAGE
14 Ld TSSOP
14 Ld TSSOP (Pb-free)
14 Ld TSSOP
14 Ld TSSOP (Pb-free)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN8203 Rev 2.00
October 17, 2005
Page 1 of 16
X9460
Simplified Functional Diagram
V
CC
Power-on
Recall
mute
data
address
I
2
C
bus
BUS
INTERFACE
CONTROL &
REGISTER
select
inc/dec
R
H-Left
R
H-Right
V+
62dB total
STEP SIZE
-1dB
POT
Left
POT
Right
# OF
STEPS
11
10
5
4
1
-2dB
-3dB
-4dB
Mute
V
SS
R
W-Left
R
L-Left
R
W-Right
R
L-Right
V-
Detailed Functional Diagram
V
CC
V+
Power-on
Recall
mute
SCL
SDA
A0
A1
INTERFACE
AND
CONTROL
CIRCUITRY
WIPER
COUNTER
REGISTER
(WCR)
POT Left
R
H-Left
R
L-Left
R
W-Left
R
W-Right
8
D ATA
WIPER
COUNTER
REGISTER
(WCR)
POT Right
R
H-Right
R
L-Right
V
SS
V-
FN8203 Rev 2.00
October 17, 2005
Page 2 of 16
X9460
Typical Application
Audio
Gain / Volume Control
Left Channel Control
Right Channel Control
Simultaneous Left and Right Channel
Control
Power-up in Mute
Audio => R
HL,
R
HR
R
WL
, R
WR
=> Amplifier
Audio
Amplifier
Right
Audio
DAC
X9460
2 XDCP
Amplifier
Left
µController
Serial Bus
EEPROM
Pin Assignments
PIN
(TSSOP)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SYMBOL
SDA
SCL
V
CC
V+
V
SS
A0
A1
R
W-left
R
L-left
R
H-left
R
W-right
R
L-right
R
H-right
V-
Serial Data
Serial Clock
System Supply Voltage
Positive Analog Supply
System Ground
Device Address
Device Address
Wiper terminal of the Left Potentiometer
Negative terminal of the Left Potentiometer
Positive terminal of the Left Potentiometer
Wiper terminal of the Right Potentiometer
Negative terminal of the Right Potentiometer
Positive terminal of the Right Potentiometer
Negative Analog Supply
FUNCTION
FN8203 Rev 2.00
October 17, 2005
Page 3 of 16
X9460
Detailed Pin Description
Host Interface Pins
SERIAL CLOCK (SCL)
The SCL input clocks data into and out of the X9460.
SERIAL DATA (SDA)
SDA is a bidirectional pin used to transfer data into and out of
the device. It is an open drain output and may be wire-ORed
with any number of open drain or open collector outputs. An
open drain output requires the use of a pull-up resistor. For
selecting typical values, refer to the guidelines for calculating
typical values on the bus pull-up resistors graph.
DEVICE ADDRESS (A
1
- A
0
)
The Address inputs are used to set the least significant 2 bits
of the 8-bit Slave Byte Address. A match in the slave address
serial data stream must be made with the Address input in
order to initiate communication with the X9460. Up to 4 X9460s
may be connected to a single I
2
C serial bus and written to
(NOTE: you cannot read from more than one device on the
same 2-wire bus). If left floating, these pins are internally pulled
to ground.
Slave Byte (bits, MSB-LSB) = 0101 0 A
1
A
0
R/W
The V
SS
pin is always connected to the system common or
ground. V
H
, V
L
, V
W
are the voltages on the R
H
, R
L
, and R
W
potentiometer pins.
X9460 Principles of Operation
The X9460 is a highly integrated microcircuit incorporating two
resistor arrays with their associated registers, counters and the
serial interface logic providing direct communication between
the host and the DCP potentiometers. This section provides
detailed description as following:
- Resistor Array Description
- Serial Interface Description
- Command Set and Register Information Description
Resistor Array Description
The X9460 is comprised of two resistor arrays. Each array
contains 31 discrete resistive segments that are connected in
series. The physical ends of each array are equivalent to the
fixed terminals of a mechanical potentiometer (R
H
and R
L
inputs). Tables 1 and 2 provide a description of the step size
and tap positions.
At both ends of each array and between each resistor segment
is a CMOS switch connected to the wiper (R
W
) output. Within
each individual array only one switch may be turned on at a
time. These switches are controlled by the Wiper Counter
Register (WCR). The five bits of the WCR are decoded to
select, and enable, one of thirty-two switches.
TABLE 1. TOTAL -62dB RANGE PLUS MUTE POSITION
STEP SIZE
-1dB
- 2dB
- 3dB
- 4dB
Mute
# OF STEPS
11 steps
10 steps
5 steps
4 steps
1 step
Potentiometer Pins
R
H-LEFT
, R
L-LEFT
, R
H-RIGHT
, R
L-RIGHT
The R
H
and R
L
inputs are equivalent to the terminal connections
on either end of a mechanical potentiometer.
R
W-LEFT
, R
W-RIGHT
The wiper outputs are equivalent to the wiper output of a
mechanical potentiometer.
Supply Pins
ANALOG SUPPLY V- AND V+
The positive power supply for the DCP analog control section
is connected to V+. The negative power supply for the DCP
analog control section is connected to V-.
DIGITAL SUPPLIES V
CC
, V
SS
The power supplies for the digital control sections.
TABLE 2. WIPER TAP POSITION vs dB
TAP POSITION, n
for n = 20 to 31
for n = 10 to 19
for n = 5 to 9
for n = 1 to 4
n=0
dB
n - 31
2n-51
3n-61
4n-66
-92
MIN/MAX dB
-11/0
-31/-13
-46/-34
-62/-50
-92
Power-up and Down Recommendations
There are no restrictions on the power-up condition of V
CC
, V+
and V- and the voltages applied to the potentiometer pins
provided that the V
CC
and V+ are more positive or equal to the
voltage at R
H
, R
L
, and R
W
, ie. V
CC
, V+ > R
H
, R
L
, R
W
. At all
times, the voltages on the potentiometer pins must be less
than V+ and more than V-.
The following V
CC
ramp rate spec is always in effect.
0.2 V/ms < V
CC
ramp < 50 V/ms
FN8203 Rev 2.00
October 17, 2005
Page 4 of 16
X9460
Serial Interface Description
Serial Interface
The X9460 supports a bidirectional bus oriented protocol. The
protocol defines any device that sends data onto the bus as a
transmitter and the receiving device as the receiver. The
device controlling the transfer is a master and the device being
controlled is the slave. The master will always initiate data
transfers and provide the clock for both transmit and receive
operations. The X9460 is a slave device in all applications.
Stop Condition
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA while SCL is HIGH.
Acknowledge
Acknowledge is a software convention used to provide a
positive handshake between the master and slave devices on
the bus to indicate the successful receipt of data. The
transmitting device, either the master or the slave, will release
the SDA bus after transmitting eight bits. The master generates
a ninth clock cycle and during this period the receiver pulls the
SDA line LOW to acknowledge that it successfully received the
eight bits of data.
The X9460 will respond with an acknowledge: 1) after
recognition of a start condition and after an identification and
slave address byte, and 2) again after each successful receipt
of the instruction or databyte. See Figure 1.
Clock and Data Conventions
Data states on the SDA line can change only during SCL LOW
periods. SDA state changes during SCL HIGH are reserved for
indicating start and stop conditions.
Start Condition
All commands to the X9460 are preceded by the start
condition, which is a HIGH to LOW transition of SDA while SCL
is HIGH. The X9460 continuously monitors the SDA and SCL
lines for the start condition and will not respond to any
command until this condition is met.
Invalid Commands
For any invalid commands or unrecognizable addresses, the
X9460 will NOT acknowledge and return the X9460 to the idle
state.
SCL FROM
MASTER
1
8
9
DATA
OUTPUT
FROM
TRANSMITTER
DATA
OUTPUT
FROM
RECEIVER
ST AR T
ACKNOWLEDGE
FIGURE 1. ACKNOWLEDGE RESPONSE FROM RECEIVER
FN8203 Rev 2.00
October 17, 2005
Page 5 of 16
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