CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation
of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Analog Specifications
SYMBOL
R
TOTAL
Over recommended operating conditions unless otherwise stated.
TEST CONDITIONS
Y, W, U, T versions respectively
-20
25°C, each DCP
0.75
See test circuit
Wiper current =
V
CC
-3.0
50
MIN
TYP
(Note 4)
2.8, 10, 50,
100
+20
50
2.0
+3.0
150
MAX
UNIT
kΩ
%
mW
%
mA
Ω
PARAMETER
End to end resistance
End to end resistance tolerance
Power rating
R
TOTAL
Matching
I
W
(Note 5)
R
W
DCP to DCP resistance matching
Wiper current
Wiper resistance
R
TOTAL
Vss
Vcc
-120
0.4
V
dBV
%
+1
+0.3
±300
-20
+20
10/10/25
0.1
10
MI (Note 3)
MI (Note 3)
ppm/°C
ppm/°C
pF
µA
V
TERM
Voltage on any DCP pin
Noise (Note 5)
Resolution
Absolute linearity (Note 1)
Relative linearity (Note 2)
Temperature coefficient of resistance
(Note 5)
Ratiometric Temperature (Note 5)
Coefficient
V(R
H0
)=V(R
H1
)=V
CC
V(R
L0
)=V(R
L1
)=V
SS
Ref: 1kHz
-1
-0.3
C
H
/C
L
/C
W
I
OL
Potentiometer Capacitance (Note 5)
Leakage on DCP pins
See equivalent circuit
Voltage at pin from V
SS
to V
CC
DC Electrical Specifications
SYMBOL
I
CC1
I
CC2
I
CC3
I
SB
I
L
Over the recommended operating conditions unless otherwise specified.
TEST CONDITIONS
f
SCL
= 400kHz; SDA = Open; (for 2-Wire, Active,
Read and Volatile Write States only)
f
SCL
= 200kHz; (for U/D interface, increment,
decrement)
f
SCL
= 400kHz; SDA = Open;
(for 2-Wire, Active, Nonvolatile Write State only)
V
CC
= +5.5V; V
IN
= V
SS
or V
CC
; SDA = V
CC
;
(for 2-Wire, Standby State only)
Voltage at pin from V
SS
to V
CC
-10
MIN
MAX
3
3
5
20
10
UNITS
mA
mA
mA
µA
µA
PARAMETER
V
CC
supply current (Volatile write/read)
V
CC
supply current (active)
V
CC
supply current (nonvolatile write)
V
CC
current (standby)
Leakage current, bus interface pins
3
FN8202.0
November 10, 2004
X9455
DC Electrical Specifications
SYMBOL
V
IH
V
IL
V
OL
Input HIGH voltage
Input LOW voltage
SDA pin output LOW voltage
I
OL
= 3mA
Over the recommended operating conditions unless otherwise specified.
(Continued)
TEST CONDITIONS
MIN
V
CC
x 0.7
-1
MAX
V
CC
+ 1
V
CC
x 0.3
0.4
UNITS
V
V
V
PARAMETER
Endurance and Data Retention
PARAMETER
Minimum endurance
Data retention
MIN
100,000
100
UNITS
Data changes per bit
Years
Capacitance
SYMBOL
TEST
TEST CONDITIONS
V
OUT
= 0V
V
IN
= 0V
MAX
8
6
UNITS
pF
pF
C
IN/OUT
(Note 5) Input / Output capacitance (SDA)
C
IN
(Note 5)
Input capacitance (DS0, DS1, CS, U/D,
SCL, WP, A2, A1
and A0
)
Power-Up Timing
SYMBOL
t
D
(Notes 5, 9)
PARAMETER
Power Up Delay from V
CC
power up (V
CC
above 2.7V) to wiper position recall
completed, and communication interfaces ready for operation.
MAX
2
UNITS
ms
A.C. Test Conditions
Input Pulse Levels
Input rise and fall times
Input and output timing threshold level
External load at pin SDA
V
CC
x 0.1 to V
CC
x 0.9
10ns
V
CC
x 0.5
2.3kΩ to V
CC
and 100 pF to V
SS
2-Wire Interface Timing (s)
SYMBOL
f
SCL
t
HIGH
t
LOW
t
SU:STA
t
HD:STA
t
SU:STO
t
SU:DAT
t
HD:DAT
t
R
(Note 5)
t
F
(Note 5)
t
AA
(Note 5)
t
DH
t
IN
(Note 5)
t
BUF
(Note 5)
Clock Frequency
Clock High Time
Clock Low Time
Start Condition Setup Time
Start Condition Hold Time
Stop Condition Setup Time
SDA Data Input Setup Time
SDA Data Input Hold Time
SCL and SDA Rise Time
SCL and SDA Fall Time
SCL Low to SDA Data Output Valid Time
SDA Data Output Hold Time
Pulse Width Suppression Time at SCL and SDA inputs
Bus Free Time (Prior to Any Transmission)
1200
0
50
600
1300
600
600
600
100
30
300
300
0.9
PARAMETER
MIN
MAX
400
UNITS
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
4
FN8202.0
November 10, 2004
X9455
2-Wire Interface Timing (s)
(Continued)
SYMBOL
t
SU:WPA
(Note 5)
t
HD:WPA
(Note 5)
A0, A1, A2 and WP Setup Time
A0, A1, A2 and WP Hold Time
PARAMETER
MIN
600
600
MAX
UNITS
ns
ns
SDA vs. SCL Timing
t
F
t
HIGH
t
LOW
t
R
SCL
t
SU:STA
SDA
(Input Timing)
t
SU:DAT
t
HD:DAT
t
SU:STO
t
HD:STA
t
AA
SDA
(Output Timing)
t
DH
t
BUF
WP, A0, A1, and A2 Pin Timing
START
SCL
STOP
Clk 1
SDA IN
t
SU:WP
WP, A0, A1, or A2
t
HD:WP
Increment/Decrement Timing
SYMBOL
t
CI
t
ID
(Note 5)
t
DI
(Note 5)
t
IL
t
IH
t
IC
t
CPHS
t
CPHNS
(Note 5)
t
IW
(Note 5)
t
CYC
t
R
, t
F
(Note 5)
CS to SCL Setup
SCL HIGH to U/D, DS0 or DS1 change
U/D, DS0 or DS1 to SCL setup
SCL LOW period
SCL HIGH period
SCL inactive to CS inactive (Nonvolatile Store Setup Time)
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