DATASHEET
X9429
Low Noise/Low Power/2-Wire Bus Single Digitally Controlled Potentiometer
(XDCP™)
The X9429 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS integrated
circuit.
The digital controlled potentiometer is implemented using 63
resistive elements in a series array. Between each element
are tap points connected to the wiper terminal through
switches. The position of the wiper on the array is controlled
by the user through the 2-wire bus interface. The
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and a four non-volatile Data Registers that
can be directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the resistor
array though the switches. Power-up recalls the contents of
the default data register (DR0) to the WCR.
The XDCP can be used as a three-terminal potentiometer or
as a two terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
FN8248
Rev 4.00
October 16, 2015
Features
• Single Voltage Potentiometer
• 64 Resistor Taps
• 2-wire Serial Interface for Write, Read, and Transfer
Operations of the Potentiometer
• Wiper Resistance, 150W Typical at 5V
• Non-Volatile Storage of Multiple Wiper Positions
• Power-on Recall. Loads Saved Wiper Position on Power-up.
• Standby Current < 3µA Max
• V
CC
: 2.7V to 5.5V Operation
• 2.5kW, 10kW Total Pot Resistance
• Endurance: 100,000 Data Changes per Bit per Register
• 100 yr. Data Retention
• 14 Ld TSSOP, 16 Ld SOIC
• Low Power CMOS
• Pb-free available (RoHS compliant)
Block Diagram
V
CC
V
H
/R
H
ADDRESS
DATA
STATUS
2-WIRE
BUS
INTERFACE
WRITE
READ
TRANSFER
INC/DEC
BUS
INTERFACE
AND
CONTROL
CONTROL
POWER-ON RECALL
WIPER COUNTER
REGISTER (WCR)
DATA REGISTERS
4 BYTES
WIPER
10k
64-TAPS
POT
V
SS
V
L
/R
L
V
W
/R
W
FN8248 Rev 4.00
October 16, 2015
Page 1 of 21
X9429
Ordering Information
PART
NUMBER
X9429WS16Z* (Note)
(No longer available,
recommended replacement:
X9429WS16IZT1)
X9429WS16IZ* (Note)
X9429WV14Z* (Note)
X9429WV14IZ* (Note)
X9429WS16Z-2.7* (Note)
(No longer available,
recommended replacement:
X9429WS16IZT1)
X9429WS16IZ-2.7* (Note)
(No longer available,
recommended replacement:
X9429WS16IZT1)
X9429WV14Z-2.7* (Note)
X9429WV14IZ-2.7* (Note)
PART
MARKING
X9429WS Z
V
CC
LIMITS
(V)
5 ±10%
POTENTIOMETER
ORGANIZATION
(kΩ)
10
TEMP
RANGE (°C)
0 to +70
PACKAGE
(RoHS Compliant)
16 Ld SOIC (300 mil)
PKG
DWG. #
M16.3
X9429WS Z I
X9429 WV Z
X9429 WV Z I
X9429WS ZF
2.7 to 5.5
10
-40 to +85
0 to +70
-40 to +85
0 to +70
16 Ld SOIC (300 mil)
M16.3
14 Ld TSSOP (4.4mm) M14.173
14 Ld TSSOP (4.4mm) M14.173
16 Ld SOIC (300 mil)
M16.3
X9429WS ZG
-40 to +85
16 Ld SOIC (300 mil)
M16.3
X9429 WVZF
X9429 WVZ G
0 to +70
-40 to +85
14 Ld TSSOP (4.4mm) M14.173
14 Ld TSSOP (4.4mm) M14.173
*Add “T1” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN8248 Rev 4.00
October 16, 2015
Page 2 of 21
X9429
Detailed Functional Diagram
V
CC
POWER-ON RECALL
DR0 DR1
WIPER
CONTROL
SCL
SDA
A3
A2
A0
WP
INTERFACE
AND
CONTROL
CIRCUITRY
D ATA
COUNTER
REGISTER
(WCR)
DR2 DR3
10k
64--TAPS
R
H
/V
H
R
L
/V
L
R
W
/V
W
V
SS
Circuit Level Applications
• Vary the Gain of a Voltage Amplifier
• Provide Programmable DC Reference Voltages for
Comparators and Detectors
• Control the Volume in Audio Circuits
• Trim Out the Offset Voltage Error in a Voltage Amplifier
Circuit
• Set the Output Voltage of a Voltage Regulator
• Trim the Resistance in Wheatstone Bridge Circuits
• Control the Gain, Characteristic Frequency and
Q-factor in Filter Circuits
• Set the Scale Factor and Zero Point in Sensor Signal
Conditioning Circuits
• Vary the Frequency and Duty Cycle of Timer ICs
• Vary the DC Biasing of a Pin Diode Attenuator in RF Circuits
• Provide a Control Variable (I, V, or R) in Feedback Circuits
System Level Applications
• Adjust the Contrast in LCD Displays
• Control the Power Level of LED Transmitters in
Communication Systems
• Set and Regulate the DC Biasing Point in an RF Power
Amplifier in Wireless Systems
• Control the Gain in Audio and Home Entertainment Systems
• Provide the Variable DC Bias for Tuners in RF Wireless
Systems
• Set the Operating Points in Temperature Control Systems
• Control the Operating Point for Sensors in Industrial
Systems
• Trim Offset and Gain Errors in Artificial Intelligent Systems
FN8248 Rev 4.00
October 16, 2015
Page 3 of 21
X9429
Pinouts
X9429
(14 LD TSSOP)
TOP VIEW
NC
NC
NC
A2
SCL
SDA
VSS
1
2
3
4
5
6
7
14
13
12
V
CC
R
L
/V
L
R
H
/V
H
R
W
/V
W
A3
A0
WP
NC
NC
NC
A2
SCL
SDA
NC
VSS
X9429
(16 LD SOIC)
TOP VIEW
1
2
3
4
5
6
7
8
16
15
14
V
CC
NC
R
L
/V
L
R
H
/V
H
R
W
/V
W
A3
A0
WP
X9429
11
10
9
8
X9429
13
12
11
10
9
Pin Assignments
TSSOP PIN
1, 2, 3
4
5
6
7
8
9
10
11
12
13
14
SOIC PIN
12, 3, 7, 15
4
5
6
8
9
10
11
12
13
14
16
SYMBOL
NC
A2
SCL
SDA
V
SS
WP
A0
A3
R
W
/V
W
R
H
/V
H
R
L
/V
L
V
CC
No Connect
Device Address for 2-wire bus.
Serial Clock for 2-wire bus.
Serial Data Input/Output for 2-wire bus.
System Ground
Hardware Write Protect
Device Address for 2-wire bus.
Device Address for 2-wire bus.
Wiper Terminal of the Potentiometer.
High Terminal of the Potentiometer.
Low Terminal of the Potentiometer.
System Supply Voltage
BRIEF DESCRIPTION
Pin Descriptions
Host Interface Pins
SERIAL CLOCK (SCL)
The SCL input is used to clock data into and out of the X9429.
SERIAL DATA (SDA)
SDA is a bidirectional pin used to transfer data into and out of
the device. It is an open drain output and may be wire-ORed
with any number of open drain or open collector outputs. An
open drain output requires the use of a pull-up resistor. For
selecting typical values, refer to the guidelines for calculating
typical values on the bus pull-up resistors graph.
DEVICE ADDRESS (A
0
, A
2
, A
3
)
The Address inputs are used to set the least significant 3 bits
of the 8-bit slave address. A match in the slave address serial
data stream must be made with the Address input in order to
initiate communication with the X9429. A maximum of 8
devices may occupy the 2-wire serial bus.
Potentiometer Pins
R
H
/V
H
, R
L
/V
L
The R
H
/V
H
and R
L
/V
L
inputs are equivalent to the terminal
connections on either end of a mechanical potentiometer.
R
W
/V
W
The wiper outputs are equivalent to the wiper output of a
mechanical potentiometer.
HARDWARE WRITE PROTECT INPUT WP
The WP pin when low prevents nonvolatile writes to the Data
Registers.
Principals of Operation
The X9429 is a highly integrated microcircuit incorporating a
resistor array and its associated registers and counters and the
serial interface logic providing direct communication between
the host and the XDCP potentiometers.
Serial Interface
The X9429 supports a bidirectional bus oriented protocol. The
protocol defines any device that sends data onto the bus as a
FN8248 Rev 4.00
October 16, 2015
Page 4 of 21
X9429
transmitter and the receiving device as the receiver. The
device controlling the transfer is a master and the device being
controlled is the slave. The master will always initiate data
transfers and provide the clock for both transmit and receive
operations. Therefore, the X9429 will be considered a slave
device in all applications.
Device Addressing
Following a start condition, the master must output the address
of the slave it is accessing. The most significant four bits of the
slave address are the device type identifier (refer to Figure 1).
For the X9429 this is fixed as 0101[B].
DEVICE TYPE
IDENTIFIER
Clock and Data Conventions
Data states on the SDA line can change only during SCL LOW
periods (t
LOW
). SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions.
0
1
0
1
A3
A2
0
A0
Start Condition
All commands to the X9429 are preceded by the start
condition, which is a HIGH to LOW transition of SDA while SCL
is HIGH (t
HIGH
). The X9429 continuously monitors the SDA
and SCL lines for the start condition and will not respond to any
command until this condition is met.
DEVICE ADDRESS
FIGURE 1. SLAVE ADDRESS
Stop Condition
All communications must be terminated by a stop condition,
which is a LOW-to-HIGH transition of SDA while SCL is HIGH.
Acknowledge
Acknowledge is a software convention used to provide a
positive handshake between the master and slave devices on
the bus to indicate the successful receipt of data. The
transmitting device, either the master or the slave, will release
the SDA bus after transmitting eight bits. The master generates
a ninth clock cycle and during this period, the receiver pulls the
SDA line LOW to acknowledge that it successfully received the
eight bits of data.
The X9429 will respond with an acknowledge after recognition
of a start condition and its slave address and once again after
successful receipt of the command byte. If the command is
followed by a data byte the X9429 will respond with a final
acknowledge.
The next four bits of the slave address are the device address.
The physical device address is defined by the state of the A
0
,
A
2
, and A
3
inputs. The X9429 compares the serial data stream
with the address input state; a successful compare of all three
address bits is required for the X9429 to respond with an
acknowledge. The A
0
, A
2
, and A
3
inputs can be actively driven
by CMOS input signals or tied to V
CC
or V
SS
.
Acknowledge Polling
The disabling of the inputs, during the internal non-volatile
write operation, can be used to take advantage of the typical
5ms EEPROM write cycle time. Once the stop condition is
issued to indicate the end of the non-volatile write command,
the X9429 initiates the internal write cycle. ACK polling can be
initiated immediately. This involves issuing the start condition
followed by the device slave address. If the X9429 is still busy
with the write operation, no ACK will be returned. If the X9429
has completed the write operation, an ACK will be returned,
and the master can then proceed with the next operation.
Instruction Structure
The next byte sent to the X9429 contains the instruction and
register pointer information. The four most significant bits are
the instruction. The next four bits point to one of four
associated registers. The format is shown in Figure 2.
REGISTER
SELECT
Array Description
The X9429 is comprised of a resistor array. The array contains
63 discrete resistive segments that are connected in series.
The physical ends of the array are equivalent to the fixed
terminals of a mechanical potentiometer (V
H
/R
H
and V
L
/R
L
inputs).
At both ends of the array and between each resistor segment
is a CMOS switch connected to the wiper (V
W
/R
W
) output.
Within each individual array only one switch may be turned on
at a time. These switches are controlled by the Wiper Counter
Register (WCR). The six bits of the WCR are decoded to
select, and enable, one of sixty-four switches.
The WCR may be written directly, or it can be changed by
transferring the contents of one of four associated Data
Registers into the WCR. These Data Registers and the WCR
can be read and written by the host system.
I3
I2
I1
I0
R1
R0
0
0
INSTRUCTIONS
FIGURE 2. INSTRUCTION BYTE FORMAT
The four high order bits define the instruction. The next two bits
(R
1
and R
0
) select one of the four registers that is to be acted
upon when a register oriented instruction is issued. Bits 0 and
1 are defined to be 0.
FN8248 Rev 4.00
October 16, 2015
Page 5 of 21
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