IS41C8512
IS41LV8512
.EATURES
512K x 8 (4-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
Extended Data-Out (EDO) Page Mode access cycle
TTL compatible inputs and outputs; tristate I/O
Refresh Interval: 1024 cycles /16 ms
Refresh Mode:
RAS-Only, CAS-before-RAS
(CBR),
Hidden
JEDEC standard pinout
Single power supply:
5V ± 10% (IS41C8512)
3.3V ± 10% (IS41LV8512)
Byte Write and Byte Read operation via
CAS
Industrail Temperature Range -40
o
C to 85
o
C
DESCRIPTION
The
1+51
IS41C8512 and IS41LV8512 is a 524,288 x 8-bit
high-performance CMOS Dynamic Random Access Memories.
The IS41C8512 offer an accelerated cycle access called EDO
Page Mode. EDO Page Mode allows 512 random accesses
within a single row with access cycle time as short as 10 ns per
8-bit.
These features make the IS41C8512and IS41LV8512 ideally
suited for high-bandwidth graphics, digital signal processing,
high-performance computing systems, and peripheral
applications.
The IS41C8512 is packaged in a 28-pin 400mil SOJ and
400mil TSOP-2.
KEY TIMING PARAMETERS
Parameter
Max.
RAS
Access Time (t
RAC
)
Max.
CAS
Access Time (t
CAC
)
Max. Column Address Access Time (t
AA
)
Min. EDO Page Mode Cycle Time (t
PC
)
Min. Read/Write Cycle Time (t
RC
)
-35
35
10
18
12
60
-50
50
14
25
20
90
-60
60
15
30
25
110
Unit
ns
ns
ns
ns
ns
PIN CON.IGURATIONS
28 Pin SOJ, TSOP-2
PIN DESCRIPTIONS
VCC
I/O0
I/O1
I/O2
I/O3
NC
WE
RAS
A9
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
I/O7
I/O6
I/O5
I/O4
CAS
OE
NC
A8
A7
A6
A5
A4
GND
A0-A9
I/O0-7
WE
OE
RAS
CAS
Vcc
GND
NC
Address Inputs
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Column Address Strobe
Power
Ground
No Connection
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
DR008-0B
1
IS41C8512
IS41LV8512
.unctional Description
The IS41C8512 and IS41LV8512 is a CMOS DRAM
optimized for high-speed bandwidth, low power
applications. During READ or WRITE cycles, each bit is
uniquely addressed through the 10 address bits. These
are entered ten bits (A0-A9) at a time. The row address is
latched by the Row Address Strobe (RAS). The column
address is latched by the Column Address Strobe (CAS).
RAS
is used to latch the first ten bits and
CAS
is used the
latter nine bits.
CAS-before-RAS
is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Extended Data Out Page Mode
EDO page mode operation permits all 512 columns within
a selected row to be randomly accessed at a high data
rate.
In EDO page mode read cycle, the data-out is held to the
next
CAS
cycles falling edge, instead of the rising edge.
.or this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the
CAS
cycle time becomes shorter. Therefore,
in EDO page mode, the timing margin in read cycle is
larger than that of the fast page mode even if the
CAS
cycle
time becomes shorter.
In EDO page mode, due to the extended data function, the
CAS
cycle time can be shorter than in the fast page mode
if the timing margin is the same.
The EDO page mode allows both read and write opera-
tions during one
RAS
cycle, but the performance is equiva-
lent to that of the fast page mode in that case.
Memory Cycle
A memory cycle is initiated by bring
RAS
LOW and it is
terminated by returning both
RAS
and
CAS
HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum t
RAS
time has expired. A new
cycle must not be initiated until the minimum precharge
time t
RP
, t
CP
has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of
CAS
or
OE,
whichever occurs last, while holding
WE
HIGH. The
column address must be held for a minimum time specified
by t
AR
. Data Out becomes valid only when t
RAC
, t
AA
, t
CAC
and t
OEA
are all satisfied. As a result, the access time is
dependent on the timing relationships between these
parameters.
Power-On
Write Cycle
A write cycle is initiated by the falling edge of
CAS
and
WE,
whichever occurs last. The input data must be valid
at or before the falling edge of
CAS
or
WE,
whichever
occurs first.
After application of the V
CC
supply, an initial pause of
200 µs is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a
RAS
signal).
During power-on, it is recommended that
RAS
track with
V
CC
or be held at a valid V
IH
to avoid current surges.
Refresh Cycle
To retain data, 1024 refresh cycles are required in each
16 ms period. There are two ways to refresh the memory.
1. By clocking each of the 1024 row addresses (A0
through A9) with
RAS
at least once every 16 ms. Any
read, write, read-modify-write or
RAS-only
cycle re-
freshes the addressed row.
2. Using a
CAS-before-RAS
refresh cycle.
CAS-before-
RAS
refresh is activated by the falling edge of
RAS,
while holding
CAS
LOW. In
CAS-before-RAS
refresh
cycle, an internal 10-bit counter provides the row ad-
dresses and the external address inputs are ignored.
Integrated Circuit Solution Inc.
DR008-0B
3
IS41C8512
IS41LV8512
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
T
V
CC
I
OUT
P
D
T
A
T
STG
Parameters
Voltage on Any Pin Relative to GND
Supply Voltage
Output Current
Power Dissipation
Commercial Operation Temperature
Industrial Operationg Temperature
Storage Temperature
5V
3.3V
5V
3.3V
Rating
1.0 to +7.0
0.5 to +4.6
1.0 to +7.0
0.5 to +4.6
50
1
0 to +70
40 to +85
55 to +125
Unit
V
V
mA
W
°C
°C
°C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltages are referenced to GND.)
Symbol
V
CC
V
IH
V
IL
T
A
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Commercial Ambient Temperature
Industrial Ambient Temperature
5V
3.3V
5V
3.3V
5V
3.3V
Min.
4.5
3.0
2.4
2.0
1.0
0.3
0
40
Typ.
5.0
3.3
Max.
5.5
3.6
V
CC
+ 1.0
V
CC
+ 0.3
0.8
0.8
70
85
Unit
V
V
V
°C
°C
CAPACITANCE
(1,2)
Symbol
C
IN
1
C
IN
2
C
IO
Parameter
Input Capacitance: A0-A8
Input Capacitance:
RAS, UCAS, LCAS, WE, OE
Data Input/Output Capacitance: I/O0-I/O15
Max.
5
7
7
Unit
p.
p.
p.
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25°C, f = 1 MHz.
4
Integrated Circuit Solution Inc.
DR008-0B
IS41C8512
IS41LV8512
ELECTRICAL CHARACTERISTICS
(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol
I
IL
I
IO
V
OH
V
OL
I
CC
1
Parameter
Input Leakage Current
Output Leakage Current
Output High Voltage Level
Output Low Voltage Level
Standby Current: TTL
Test Condition
Any input 0V < V
IN
< Vcc
Other inputs not under test = 0V
Output is disabled (Hi-Z)
0V < V
OUT
< Vcc
I
OH
= 2.5 mA
I
OL
=+2.1mA
RAS, CAS
> V
IH
Commerical
Industrial
Commerical
Industrial
5V
5V
3V
3V
5V
3V
-35
-50
-60
-35
-50
-60
-35
-50
-60
-35
-50
-60
Speed
Min.
10
10
2.4
Max.
10
10
0.4
3
4
2
3
2
1
230
180
170
220
170
160
230
180
170
230
180
170
Unit
µA
µA
V
V
mA
I
CC
2
I
CC
3
Standby Current: CMOS
Operating Current:
Random Read/Write
(2,3,4)
Average Power Supply Current
Operating Current:
EDO Page Mode
(2,3,4)
Average Power Supply Current
Refresh Current:
RAS-Only
(2,3)
Average Power Supply Current
Refresh Current:
CBR
(2,3,5)
Average Power Supply Current
RAS, CAS
> V
CC
0.2V
RAS, CAS,
Address Cycling, t
RC
= t
RC
(min.)
RAS
= V
IL
,
CAS,
Cycling t
PC
= t
PC
(min.)
RAS
Cycling,
CAS
> V
IH
t
RC
= t
RC
(min.)
RAS, CAS
Cycling
t
RC
= t
RC
(min.)
mA
mA
I
CC
4
mA
I
CC
5
mA
I
CC
6
mA
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight
RAS
refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight
RAS
cycles wake-up should be repeated any time the t
RE.
refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
Integrated Circuit Solution Inc.
DR008-0B
5
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