February 2010
Includes
High-
,
Performance
Low-Cost
“E-Series”
ispXPGA Family
®
Data Sheet DS1026
Non-volatile, Infinitely Reconfigurable
• Instant-on - Powers up in microseconds via
on-chip E
2
CMOS
®
based memory
• No external configuration memory
• Excellent design security, no bit stream to intercept
• Reconfigure SRAM based logic in milliseconds
• Microprocessor configuration interface
• Program E
2
CMOS while operating from SRAM
SE
LE
D
IS C
C T
O D
N E
TI VI
N C
U E
ED S
High Logic Density for System-level
Integration
•
•
•
•
139K to 1.25M functional gates
160 to 496 I/O
1.8V, 2.5V, and 3.3V V
CC
operation
Up to 414Kb sysMEM™ embedded memory
•
•
•
•
•
True PLL technology
10MHz to 320MHz operation
Clock multiplication and division
Phase adjustment
Shift clocks in 250ps steps
Eight sysCLOCK™ Phase Locked Loops
(PLLs) for Clock Management
sysIO™ for High System Performance
High Performance Programmable Function
Unit (PFU)
• Four LUT-4 per PFU supports wide and narrow
functions
• Dual flip-flops per LUT-4 for extensive pipelining
• Dedicated logic for adders, multipliers, multiplex-
ers, and counters
• Multiple sysMEM Embedded RAM Blocks
– Single port, Dual port, and FIFO operation
• 64-bit distributed memory in each PFU
– Single port, Double port, FIFO, and Shift
Register operation
Flexible Memory Resources
• High speed memory support through SSTL and
HSTL
• Advanced buses supported through PCI, GTL+,
LVDS, BLVDS, and LVPECL
• Standard logic supported through LVTTL,
LVCMOS 3.3, 2.5 and 1.8
• 5V tolerant I/O for LVCMOS 3.3 and LVTTL
interfaces
• Programmable drive strength for series termination
• Programmable bus maintenance
• High-performance sysHSI (standard part number)
• Low-cost, no sysHSI (“E-Series”)
Two Options Available
Flexible Programming, Reconfiguration,
and Testing
• Supports IEEE 1532 and 1149.1
sysHSI™ Capability for Ultra Fast Serial
Communications
• Up to 800Mbps performance
• Up to 20 channels per device
• Built in Clock Data Recovery (CDR) and
Serialization and De-serialization (SERDES)
ispXPGA 500/E
476K
1764
7056
ispXPGA 1200/E
3
1.25M
3844
Table 1. ispXPGA Family Selection Guide
Functional Gates
ispXPGA 125/E
139K
484
1936
3.8K
92K
30K
20
4
ispXPGA 200/E
210K
676
2704
5.4K
43K
24
8
PFUs
LUT-4s
15376
30.7K
414K
90
20
246K
Logic FFs
14.1K
184K
40
112K
12
sysMEM Memory
EBR
111K
Distributed Memory
sysHSI Channels
1
User I/O
Packaging
160/176
256 fpBGA
516 fpBGA
2
160/208
256 fpBGA
516 fpBGA
2
336
516 fpBGA
2
900 fpBGA
496
680 fpSBGA
900 fpBGA
1. “E-Series” does not support sysHSI.
2. FH516 package was converted to F516 via
PCN #09A-08.
3. Discontinued via
PCN #03A-10.
© 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1
DS1026_15.0
stm32/stm8
京公网安备 11010802033920号
EEWORLD
