GS815036AGB-333T datasheet, PDF

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GS815036AGB-333T: DescriptionLate-Write SRAM, 512KX36, 1.5ns, CMOS, PBGA119, ROHS COMPLIANT, FBGA-119; Categorystorage storage; File Size337KB，23 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/; Environmental Compliance

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GS815036AGB-333T Overview

Late-Write SRAM, 512KX36, 1.5ns, CMOS, PBGA119, ROHS COMPLIANT, FBGA-119

GS815036AGB-333T Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	GSI Technology
Parts packaging code	BGA
package instruction	BGA,
Contacts	119
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Maximum access time	1.5 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B119
JESD-609 code	e1
length	22 mm
memory density	18874368 bit
Memory IC Type	LATE-WRITE SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	119
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512KX36
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.99 mm
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm

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GS815036AB-357/333/300/250

119-Bump BGA

Commercial Temp

Industrial Temp

Features

• Register-Register Late Write mode, Pipelined Read mode

• 2.5 V +200/–200 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• ZQ controlled programmable output drivers

• Dual Cycle Deselect

• Fully coherent read and write pipelines

• Byte write operation (9-bit bytes)

• Differential HSTL clock inputs, K and K

• Asynchronous output enable

• Sleep mode via ZZ

• IEEE 1149.1 JTAG-compliant Serial Boundary Scan

• JEDEC-standard 119-bump BGA package

• RoHS-compliant 119-bump BGA package available

512K x 36

18Mb Register-Register Late Write SRAM

Functional Description

250 MHz–357 MHz

2.5 V V

1.5 V or 1.8 V HSTL I/O

Because GS815036A is a synchronous device, address data

inputs and read/write control inputs are captured on the rising

edge of the input clock. Write cycles are internally self-timed

and initiated by the rising edge of the clock input. This feature

eliminates complex off-chip write pulse generation required by

asynchronous SRAMs and simplifies input signal timing.

GS815036A supports pipelined reads utilizing a rising-edge-

triggered output register. It also utilizes a Dual Cycle Deselect

(DCD) output deselect protocol.

GS815036A is implemented with high performance HSTL

technology and is packaged in a 119-bump BGA.

Family Overview

GS815036A is a 18,874,368-bit (18Mb) high performance

SRAM. This family of wide, low voltage HSTL I/O SRAMs is

designed to operate at the speeds needed to implement

economical high performance cache systems.

Mode Control

There are two mode control select pins (M1 and M2), which

allow the user to set the correct read protocol for the design.

The GS815036A supports single clock Pipeline mode, which

directly affects the two mode control select pins. In order for

the part to fuction correctly, and as specified, M1 must be tied

to V

and M2 must be tied to V

or V

DDQ

. This must be set

at power-up and should not be changed during operation.

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High)

of the ZZ signal, or by stopping the clock (CK). Memory data is

retained during Sleep mode.

Parameter Synopsis

-357

Pipeline

Cycle

tKHQV

Curr (x36)

2.8

1.4

650

-333

3.0

1.5

600

-300

3.3

1.6

550

-250

4.0

2.0

500

Unit

Rev: 1.09 1/2013

1/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS815036AB-357/333/300/250

Read Operations

Pipelined Read

A read cycle begins when the RAM captures logic 0 on SS and logic 1 on SW at the rising edge of K (and the falling edge of K).

Address inputs captured on that clock edge are propigated into the RAM, which delivers data to the input of the output registers.

The second rising edge of K fires the output registers and releases read data to the output drivers. If G is held active low, the

drivers drive the data onto the output pins. Read data is sustained on the output pins as long as G is held low or until the next rising

edge of K, at which point the outputs may update to new data or deselect, depending on what control command was registered at

the second rising edge of K.

Dual Cycle Deselect

Chip deselect (SS = logic 1) is pipelined to the same degree as read data. Therefore, a deselect command entered on the rising edge

of K is acted upon in response to the next rising edge of K.

Write Operations

Write operations are initiated when the write enable input signal (SW) and chip select (SS) are captured at logic 0 on a rising edge

of the K clock (and falling edge of the K clock).

Late Write

In Late Write mode the RAM requires Data In one rising clock edge later than the edge used to load Address and Control. Late

Write protocol has been employed on SRAMs designed for RISC processor L2 cache applications and in Flow Through mode NBT

SRAMs.

Byte Write Control

The Byte Write Enable inputs (Bx) determine which bytes will be written. Any combination of Byte Write Enable control pins,

including all or none, may be activated. A Write Cycle with no Byte Write inputs active is a write abort cycle. Byte write control

inputs are captured by the same clock edge used to capture SW.

Example of x36 Byte Write Truth Table

Function

Read

Write Byte A

Write Byte B

Write Byte C

Write Byte D

Write all Bytes

Write Abort

FLXDrive-II™ HSTL Output Driver Impedance Control

HSTL I/O SigmaRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to V

via an

external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value

of the desired SRAM driver impedance. The allowable range of RQ to guarantee impedance matching with specified tolerance is

between 150Ω and 300Ω. Periodic readjustment of the output driver impedance occurs automatically because driver impedance is

affected by drifts in supply voltage and die temperature. A clock cycle counter periodically triggers an impedance evaluation,

resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the

optimum level. The output driver is implemented with discrete binary weighted impedance steps. The SRAM requires 32K start-up

clock cycles, selected or deselected, after V

reaches its operating range to reach its programmed output driver impedance.

Rev: 1.09 1/2013

4/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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