®
CMOS STATIC RAMs
64K (16K x 4-BIT)
Added Chip Select and Output Controls
IDT7198S
IDT7198L
Integrated Device Technology, Inc.
FEATURES:
• Fast Output Enable (
OE
) pin available for added system
flexibility
• Multiple Chip Selects (
CS
1
,
CS
2
) simplify system design
and operation
• High speed (equal access and cycle times)
— Military: 20/25/35/45/55/70/85ns (max.)
• Low power consumption
• Battery back-up operation—2V data retention (L version
only)
• 24-pin CERDIP, high-density 28-pin leadless chip carrier,
and 24-pin CERPACK packaging available
• Produced with advanced CMOS technology
• Bidirectional data inputs and outputs
• Inputs/outputs TTL-compatible
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT7198 is a 65,536 bit high-speed static RAM orga-
nized as 16K x 4. It is fabricated using IDT’s high-perfor-
mance, high-reliability technology—CMOS. This state-of-the-
art technology, combined with innovative circuit design tech-
niques, provides a cost effective approach for memory inten-
sive applications.
Access times as fast as 20ns are available. The IDT7198
offers a reduced power standby mode, I
SB1
, which is activated
when
CS
1
or
CS
2
goes HIGH. This capability decreases
power, while enhancing system reliability. The low-power
version (L) also offers a battery backup data retention capa-
bility where the circuit typically consumes only 30µW when
operating from a 2V battery.
All inputs and outputs are TTL-compatible and operate
from a single 5V supply.
The lDT7198 is packaged in either a 24-pin ceramic DlP,
28-pin leadless chip carrier, and 24-pin CERPACK.
Military grade product is manufactured in compliance with
the latest revision of MIL-STD-883, Class B, making it ideally
suited to military temperature applications demanding the
highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
A
0
V
CC
GND
DECODER
65,536-BIT
MEMORY ARRAY
A
13
I/O
0
I/O
1
I/O
2
I/O
3
COLUMN I/O
INPUT
DATA
CONTROL
CS
1
CS
2
WE
1
OE
2985 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY TEMPERATURE RANGE
©1994
Integrated Device Technology, Inc.
MAY 1994
6.4
DSC-1027/4
1
IDT7198S/L
CMOS STATIC RAM 64K (16K x 4-BIT) Added Chip Select and Output Enable Controls
MILITARY TEMPERATURE RANGE
MEMORY CONTROL
The IDT7198 64K high-speed CMOS static RAM incorpo-
rates two additional memory control features (an extra chip
select and an output enable pin) which offer additional ben-
efits in many system memory applications.
Both chip selects, Chip Select 1 (
CS
1
) and Chip Select 2
(
CS
2
), must be LOW to select the memory. If either chip select
is pulled HIGH, the memory will be deselected and remain in
the standby mode. This dual chip select feature (
CS
1
,
CS
2
)
also brings the convenience of improved system speeds to the
large memory designer by reducing the external logic required
to perform decoding.
PIN DESCRIPTIONS
Name
A
0
–A
13
CS
1
CS
2
WE
OE
Description
Address Inputs
Chip Select 1
Chip Select 2
Write Enable
Output Enable
Data I/O
Power
Ground
2985 tbl 01
I/O
0–
I/O
3
V
CC
GND
PIN CONFIGURATIONS
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
CS
1
OE
TRUTH TABLE
(1)
Mode
CS
1
CS
2
WE
OE
I/O
High-Z
High-Z
D
OUT
D
IN
High-Z
Power
Standby
Standby
Active
Active
Active
2985 tbl 02
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
D24-1
E24-1
19
18
17
16
15
16
15
V
CC
A
13
A
12
A
11
A
10
A
9
CS
2
Standby
Standby
Read
Write
Read
H
X
L
L
L
X
H
L
L
L
X
X
H
L
H
X
X
L
X
H
I/O
3
I/O
2
I/O
1
I/O
0
WE
NOTE:
1. H = V
IH
, L = V
IL
, X = don't care.
GND
2985 drw 02
DIP/SOJ/CERPACK
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
A
Rating
Terminal Voltage
with Respect to GND
Operating Temperature
Temperature
Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Mil.
–0.5 to +7.0
–55 to +125
–65 to +135
–65 to +150
1.0
50
Unit
V
°C
°C
°C
W
mA
INDEX
A
0
NC
NC
V
CC
NC
T
BIAS
T
STG
3
2
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
CS
1
4
5
6
7
8
9
10
11
1
28 27
26
25
24
23
L28-2
22
21
20
19
18
12
13 14 15 16 17
NC
A
13
A
12
A
11
A
10
A
9
I/O
3
I/O
2
I/O
1
2985 drw 03
P
T
I
OUT
NOTE:
2985 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect reliability.
OE
GND
CS
2
WE
I/O
0
LCC
TOP VIEW
6.4
2
IDT7198S/L
CMOS STATIC RAMS 64K (16K x 4-BIT) Added Chip Select and Output Enable Controls
MILITARY TEMPERATURE RANGE
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
–0.5
(1)
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Max. Unit
5.5
0
6.0
0.8
V
V
V
V
Grade
Military
Ambient Temperature
–55°C to +125°C
GND
0V
V
CC
5V
±
10%
2985 tbl 06
Typ.
5.0
0
—
—
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz, V
CC
= 0V)
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
7
7
Unit
pF
pF
NOTE:
2985 tbl 05
1. V
IL
(min.) = -3.0V for pulse width less than 20ns, once per cycle.
NOTE:
2985 tbl 04
1. This parameter is determined by device characterization, but is not
production tested.
DC ELECTRICAL CHARACTERISTICS
V
CC
= 5.0V
±
10%, Military Temperature Range Only
IDT7198S
Symbol
|I
LI
|
|I
LO
|
V
OL
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
Test Condition
V
CC
= Max.,
V
IN
= GND to V
CC
V
CC
= Max.,
CS
= V
IH,
V
OUT
= GND to V
CC
I
OL
= 10mA, V
CC
= Min.
I
OL
= 8mA, V
CC
= Min.
V
OH
Output High Voltage
I
OH
= –4mA, V
CC
= Min.
—
2.4
Min.
—
—
Max.
10
10
0.5
0.4
—
IDT7198L
Min.
—
—
—
—
2.4
Max.
5
5
0.5
0.4
—
V
2985 tbl 07
Unit
µA
µA
V
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
2985 tbl 10
5V
480Ω
DATA
OUT
255Ω
30pF*
5V
480Ω
DATA
OUT
255Ω
5pF*
2985 drw 05
2985 drw 06
Figure 1. AC Test Load
Figure 2. AC Test Load
(for t
CLZ1, 2
, t
OLZ
, t
CHZ1, 2
, t
OHZ
, t
OW
and t
WHZ
)
*Includes scope and jig capacitances
6.4
3
IDT7198S/L
CMOS STATIC RAM 64K (16K x 4-BIT) Added Chip Select and Output Enable Controls
MILITARY TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS
(1)
(V
CC
= 5V
±
10%, V
LC
= 0.2V, V
HC
= V
CC
- 0.2V)
7198S20
7198L20
Symbol
I
CC1
Parameter
Operating Power
Supply Current,
CS
1
and
CS
2
≤
V
IL
, Outputs Open
V
CC
= Max., f = 0
(2)
Dynamic Operating
Current,
CS
1
and
CS
2
≤
V
IL
, Outputs Open
V
CC
= Max., f = f
MAX(2)
Standby Power Supply
Current (TTL Level),
CS
1
or
CS
2
≥
V
IH
, V
CC
= Max.,
Outputs Open, f = f
MAX(2)
Full Standby Power
Supply Current (CMOS
Level)
CS
1
or
CS
2
≥
V
HC
,
V
CC
= Max., V
IN
≥
V
HC
or
V
IN
≤
V
LC
, f = 0
(2)
Power
S
L
S
L
S
L
S
Military
105
80
160
130
70
50
25
7198S25
7198L25
Military
105
80
155
120
60
40
20
7198S35
7198L35
Military
105
80
140
115
50
35
20
7198S45 7198S55/70 7198S85
7198L45 7198L55/70 7198L85
Military
105
80
140
110
50
35
20
Military
105
80
140
110
50
35
20
Military
105
80
140
105
50
35
20
mA
mA
mA
Unit
mA
I
CC2
I
SB
I
SB1
L
1.5
1.5
1.5
1.5
1.5
1.5
2985 tbl 06
NOTES:
1. All values are maximum guaranteed values.
2. At f = f
MAX
address and data inputs are cycling at the maximum frequency of read cycles of 1/t
RC
. f = 0 means no input lines change.
DATA RETENTION CHARACTERISTICS OVER MILITARY TEMPERATURE RANGE
(L Version Only) V
LC
= 0.2V, V
HC
= V
CC
- 0.2V
Typ.
(1)
V
CC
@
Symbol
V
DR
I
CCDR
t
CDR
t
R(3)
|I
LI
|
(3)
(3)
Max.
V
CC
@
2.0V
—
600
—
—
2
3.0V
—
900
—
—
2
Unit
V
µA
ns
ns
µA
2985 tbl 09
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
Input Leakage Current
Test Condition
—
CS
1
Min.
2.0
—
0
t
RC(2)
—
2.0v
—
10
—
—
—
3.0V
—
15
—
—
—
or
CS
2
≥
V
HC
V
IN
≥
V
HC
or
≤
V
LC
NOTES:
1. T
A
= +25°C.
2. t
RC
= Read Cycle Time.
3. This parameter is guaranteed by device characterization but is not production tested.
LOW V
CC
DATA RETENTION WAVEFORM
DATA
RETENTION
MODE
V
DR
≥
2V
V
IH
V
DR
V
IH
2985 drw 04
V
CC
t
CDR
CS
4.5V
4.5V
t
R
6.4
4
IDT7198S/L
CMOS STATIC RAMS 64K (16K x 4-BIT) Added Chip Select and Output Enable Controls
MILITARY TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5.0V
±
10%, Military Temperature Range)
7198S20
7198L20
Symbol
Read Cycle
t
RC
t
AA
Read Cycle Time
Address Access Time
20
—
—
5
—
5
—
—
5
0
—
—
19
20
—
9
—
8
8
—
—
20
25
—
—
5
—
5
—
—
5
0
—
—
25
25
—
11
—
10
9
—
—
25
35/45
—
—
5
—
5
—
—
5
0
—
—
55
—
55
55
—
35
—
20
20
—
—
55
70
—
—
5
—
5
—
—
5
0
—
—
70
70
—
45
—
25
25
—
—
70
85
—
—
5
—
5
—
—
5
0
—
—
85
85
—
55
—
30
30
—
—
85
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2985 tbl 11
7198S25
7198L25
7198S35/45
7198L35/45
7198S55
7198L55
7198S70
7198L70
7198S85
7198L85
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
35/45 —
35/45 —
—
5
t
ACS1,2(1)
Chip Select-1,2 Access Time
t
CLZ1,2(2)
Chip Select-1,2 to Output in Low-Z
t
OE
t
OLZ(2)
t
OHZ(2)
t
OH
t
PU(2)
t
PD(2)
Output Enable to Output Valid
Output Enable to Output in Low-Z
20/25 —
—
14
15
—
—
5
—
—
5
0
t
CHZ1,2(2)
Chip Select 1,2 to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
Chip Select to Power Up Time
Chip Deselect to Power Down Time
35/45 —
NOTES:
1. Both chip selects must be active low for the device to be selected.
2. This parameter is guaranteed by device characterization but is not production tested.
TIMING WAVEFORM OF READ CYCLE NO. 1
(1)
t
RC
ADDRESS
t
AA
OE
t
OH
t
OLZ
CS
1,
t
OE
(5)
t
OHZ
(5)
2
t
ACS1, 2
t
CLZ1, 2
DATA
OUT
(5)
t
CHZ1, 2
DATA VALID
(5)
2985 drw 07
NOTES:
1.
WE
is HIGH for Read cycle.
2. Device is continuously selected,
CS
1
is LOW,
CS
2
is LOW.
3. Address valid prior to or coincident with
CS
1
and or
CS
2
transition LOW.
4.
OE
is LOW.
5. Transition is measured
±200mV
from steady state voltage.
6.4
5
Embedded System
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