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CD4081BCN_NL

Description
AND Gate, CMOS, PDIP14
Categorylogic    logic   
File Size98KB,7 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Environmental Compliance
Download Datasheet Parametric Compare View All

CD4081BCN_NL Overview

AND Gate, CMOS, PDIP14

CD4081BCN_NL Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerFairchild
package instructionDIP, DIP14,.3
Reach Compliance Codeunknown
JESD-30 codeR-PDIP-T14
Load capacitance (CL)50 pF
Logic integrated circuit typeAND GATE
Number of terminals14
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP14,.3
Package shapeRECTANGULAR
Package formIN-LINE
power supply5/15 V
Prop。Delay @ Nom-Sup250 ns
Certification statusNot Qualified
Schmitt triggerNO
surface mountNO
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
CD4071BC • CD4081BC Quad 2-Input OR Buffered B Series Gate • Quad 2-Input AND Buffered B Series Gate
October 1987
Revised April 2002
CD4071BC • CD4081BC
Quad 2-Input OR Buffered B Series Gate •
Quad 2-Input AND Buffered B Series Gate
General Description
The CD4071BC and CD4081BC quad gates are monolithic
complementary MOS (CMOS) integrated circuits con-
structed with N- and P-channel enhancement mode tran-
sistors. They have equal source and sink current
capabilities and conform to standard B series output drive.
The devices also have buffered outputs which improve
transfer characteristics by providing very high gain.
All inputs protected against static discharge with diodes to
V
DD
and V
SS
.
Features
s
Low power TTL compatibility:
Fan out of 2 driving 74L or 1 driving 74LS
s
5V–10V–15V parametric ratings
s
Symmetrical output characteristics
s
Maximum input leakage 1
µ
A at 15V over full
temperature range
Ordering Code:
Order Number
CD4071BCM
CD4071BCN
CD4081BCM
CD4081BCN
Package Number
M14A
N14A
M14A
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices are also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
CD4071B
CD4081B
Top View
Top View
© 2002 Fairchild Semiconductor Corporation
DS005977
www.fairchildsemi.com

CD4081BCN_NL Related Products

CD4081BCN_NL CD4071BCN_NL
Description AND Gate, CMOS, PDIP14 OR Gate, CMOS, PDIP14,
Is it Rohs certified? conform to conform to
Maker Fairchild Fairchild
package instruction DIP, DIP14,.3 DIP, DIP14,.3
Reach Compliance Code unknown compliant
JESD-30 code R-PDIP-T14 R-PDIP-T14
Load capacitance (CL) 50 pF 50 pF
Logic integrated circuit type AND GATE OR GATE
Number of terminals 14 14
Maximum operating temperature 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code DIP DIP
Encapsulate equivalent code DIP14,.3 DIP14,.3
Package shape RECTANGULAR RECTANGULAR
Package form IN-LINE IN-LINE
power supply 5/15 V 5/15 V
Prop。Delay @ Nom-Sup 250 ns 250 ns
Certification status Not Qualified Not Qualified
Schmitt trigger NO NO
surface mount NO NO
technology CMOS CMOS
Temperature level INDUSTRIAL INDUSTRIAL
Terminal form THROUGH-HOLE THROUGH-HOLE
Terminal pitch 2.54 mm 2.54 mm
Terminal location DUAL DUAL
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