When WEN2/LD is held LOW during Reset, this pin is the load
(LD) enable for flag offset programming. In this configuration,
WEN2/LD can be used to access the four 8-bit offset registers
contained in the CY7C42X1 for writing or reading data to these
registers.
When the device is configured for programmable flags and
both WEN2/LD and WEN1 are LOW, the first LOW-to-HIGH
transition of WCLK writes data from the data inputs to the
empty offset least significant bit (LSB) register. The second,
third, and fourth LOW-to-HIGH transitions of WCLK store data
in the empty offset most significant bit (MSB) register, full
offset LSB register, and full offset MSB register, respectively,
when WEN2/LD and WEN1 are LOW. The fifth LOW-to-HIGH
transition of WCLK while WEN2/LD and WEN1 are LOW
writes data to the empty LSB register again.
Figure 1
shows
the registers sizes and default values for the various device
types.
It is not necessary to write to all the offset registers at one time.
A subset of the offset registers can be written; then by bringing
the WEN2/LD input HIGH, the FIFO is returned to normal
Read and Write operation. The next time WEN2/LD is brought
LOW, a Write operation stores data in the next offset register
in sequence.
The contents of the offset registers can be read to the data
outputs when WEN2/LD is LOW and both REN1 and REN2
are LOW. LOW-to-HIGH transitions of RCLK Read register
contents to the data outputs. Writes and reads should not be
preformed simultaneously on the offset registers.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS)
cycle. This causes the FIFO to enter the Empty condition
signified by EF being LOW. All data outputs (Q
0–8
) go LOW
t
RSF
after the rising edge of RS. In order for the FIFO to reset
to its default state, a falling edge must occur on RS and the
user must not read or Write while RS is LOW. All flags are
guaranteed to be valid t
RSF
after RS is taken LOW.
FIFO Operation
When the WEN1 signal is active LOW and WEN2 is active HIGH,
data present on the D
0–8
pins is written into the FIFO on each
rising edge of the WCLK signal. Similarly, when the REN1 and
REN2 signals are active LOW, data in the FIFO memory will
be presented on the Q
0–8
outputs. New data will be presented
on each rising edge of RCLK while REN1 and REN2 are
active. REN1 and REN2 must set up t
ENS
before RCLK for it
to be a valid Read function. WEN1 and WEN2 must occur t
ENS
before WCLK for it to be a valid Write function.
An output enable (OE) pin is provided to three-state the Q
0–8
outputs when OE is asserted. When OE is enabled (LOW),
data in the output register will be available to the Q
0–8
outputs
after t
OE
.
The FIFO contains overflow circuitry to disallow additional
writes when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
Document #: 38-06016 Rev. *C
Page 3 of 19
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
64 × 9
8
6 5
0
8
256 × 9
7
Empty Offset (LSB) Reg.
Default Value = 007h
512 × 9
0
8
7
Empty Offset (LSB) Reg.
Default Value = 007h
1K × 9
0
8
7
Empty Offset (LSB) Reg.
Default Value = 007h
0
Empty Offset (LSB) Reg.
Default Value = 007h
8
0
8
0
8
1
(MSB)
0
0
8
1
(MSB)
00
0
8
6 5
Full Offset (LSB) Reg
Default Value = 007h
0
8
7
Full Offset (LSB) Reg
Default Value = 007h
0
8
7
Full Offset (LSB) Reg
Default Value = 007h
0
8
7
Full Offset (LSB) Reg
Default Value = 007h
0
8
0
8
0
8
1
(MSB)
0
0
8
1
(MSB)
00
0
2K × 9
8
7
Empty Offset (LSB) Reg.
Default Value = 007h
4K × 9
0
8
7
Empty Offset (LSB) Reg.
Default Value = 007h
8K × 9
0
8
7
Empty Offset (LSB) Reg.
Default Value = 007h
0
8
2
(MSB)
000
0
8
3
(MSB)
0000
0
8
4
(MSB)
00000
0
8
7
Full Offset (LSB) Reg
Default Value = 007h
0
8
7
Full Offset (LSB) Reg
Default Value = 007h
0
8
7
Full Offset (LSB) Reg
Default Value = 007h
0
8
2
(MSB)
000
0
8
3
(MSB)
0000
0
8
4
(MSB)
00000
0
Figure 1. Offset Register Location and Default Values
Document #: 38-06016 Rev. *C
Page 4 of 19
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Programmable Flag (PAE, PAF) Operation
Whether the flag offset registers are programmed as
described in
Table 1
or the default values are used, the
programmable almost-empty flag (PAE) and programmable
almost-full flag (PAF) states are determined by their corre-
sponding offset registers and the difference between the Read
and Write pointers.
The number formed by the empty offset least significant bit
register and empty offset most significant register is referred
to as
n
and determines the operation of PAE. PAE is synchro-
nized to the LOW-to-HIGH transition of RCLK by one flip-flop
and is LOW when the FIFO contains n or fewer unread words.
PAE is set HIGH by the LOW-to-HIGH transition of RCLK
when the FIFO contains (n + 1) or greater unread words.
The number formed by the full offset least significant bit
register and full offset most significant bit register is referred to
as
m
and determines the operation of PAF. PAE is synchro-
nized to the LOW-to-HIGH transition of WCLK by one flip-flop
and is set LOW when the number of unread words in the FIFO
is greater than or equal to CY7C4421. (64 – m), CY7C4201
Table 2. Status Flags
Number of Words in FIFO
CY7C4421
0
1 to n
[2]
(n + 1) to 32
33 to (64 – (m + 1))
(64 – m)
[3]
to 63
64
0
1 to n
[2]
(n + 1) to 128
129 to (256 – (m + 1))
(256 – m)
[3]
to 255
256
CY7C4201
0
1 to n
[2]
(n + 1) to 256
257 to (512 – (m + 1))
(512 – m)
[3]
to 511
512
Number of Words in FIFO
CY7C4221
0
1 to n
[2]
(n + 1) to 512
(1024 – m)
[3]
to 1023
1024
0
1 to n
[2]
(n + 1) to 1024
(2048 – m)
[3]
to 2047
2048
CY7C4231
0
1 to n
[2]
(n + 1) to 2048
(4096 – m)
[3]
to 4095
4096
CY7C4241
0
1 to n
[2]
(n + 1) to 4096
(8192 – m)
[3]
to 8191
8192
CY7C4251
FF
H
H
H
H
H
L
PAF
H
H
H
H
L
L
PAE
L
L
H
H
H
H
EF
L
H
H
H
H
H
CY7C4211
FF
H
H
H
H
H
L
PAF
H
H
H
H
L
L
PAE
L
L
H
H
H
H
EF
L
H
H
H
H
H
(256 – m), CY7C4211 (512 – m), CY7C4221 (1K – m),
CY7C4231 (2K – m), CY7C4241 (4K – m), and CY7C4251
(8K – m). PAF is set HIGH by the LOW-to-HIGH transition of
WCLK when the number of available memory locations is
greater than m.
Table 1. Writing the Offset Registers
LD
0
WEN
0
WCLK
[1]
Selection
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
No Operation
Write Into FIFO
No Operation
0
1
1
1
0
1
513 to (1024 – (m + 1)) 1025 to (2048 – (m + 1)) 2049 to (4096 – (m + 1)) 4097 to (8192 – (m + 1))
Notes:
1. The same selection sequence applies to reading from the registers. REN1 and REN2 are enabled and a Read is performed on the LOW-to-HIGH transition of
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