IDT72205 datasheet, PDF - EEWORLD Datasheet

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IDT72205: Description256 X 18 OTHER FIFO, 15 ns, PQFP64; Categorystorage; File Size123KB，16 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/

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IDT72205 Overview

256 X 18 OTHER FIFO, 15 ns, PQFP64

IDT72205 Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	64
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	5.5 V
Minimum supply/operating voltage	4.5 V
Rated supply voltage	5 V
maximum access time	15 ns
Processing package description	Plastic, TQFP-64
state	ACTIVE
Craftsmanship	CMOS
packaging shape	SQUARE
Package Size	FLATPACK, low PROFILE
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	0.8000 mm
terminal coating	tin lead
Terminal location	Four
Packaging Materials	Plastic/Epoxy
Temperature level	INDUSTRIAL
memory width	18
organize	256 × 18
storage density	4608 deg
operating mode	Synchronize
Number of digits	256 words
Number of digits	256
cycle	25 ns
Output enable	Yes
Memory IC type	Other first in first out

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IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™

256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18

Commercial And Industrial Temperature Ranges

CMOS SyncFIFO™

256 x 18, 512 x 18, 1,024 x 18,

2,048 x 18 and 4,096 x 18

Integrated Device Technology, Inc.

IDT72205LB

IDT72215LB

IDT72225LB

IDT72235LB

IDT72245LB

FEATURES:

•

256 x 18-bit organization array (IDT72205LB)

512 x 18-bit organization array (IDT72215LB)

1,024 x 18-bit organization array (IDT72225LB)

2,048 x 18-bit organization array (IDT72235LB)

4,096 x 18-bit organization array (IDT72245LB)

10 ns read/write cycle time

Empty and Full flags signal FIFO status

Easily expandable in depth and width

Asynchronous or coincident read and write clocks

Programmable Almost-Empty and Almost-Full flags with

default settings

Half-Full flag capability

Dual-Port zero fall-through time architecture

Output enable puts output data bus in high-impedance

state

High-performance submicron CMOS technology

Available in a 64-lead thin quad flatpack (TQFP/STQFP)

and plastic leaded chip carrier (PLCC)

Industrial temperature range (–40

C to +85

C) is available

DESCRIPTION:

The IDT72205LB/72215LB/72225LB/72235LB/72245LB

are very high-speed, low-power First-In, First-Out (FIFO)

memories with clocked read and write controls. These FIFOs

are applicable for a wide variety of data buffering needs, such

as optical disk controllers, Local Area Networks (LANs), and

interprocessor communication.

These FIFOs have 18-bit input and output ports. The input

port is controlled by a free-running clock (WCLK), and an input

enable pin (

WEN

). Data is read into the synchronous FIFO on

every clock when

WEN

is asserted. The output port is controlled

by another clock pin (RCLK) and another enable pin (

REN

). The

read clock can be tied to the write clock for single clock

operation or the two clocks can run asynchronous of one

another for dual-clock operation. An Output Enable pin (

) is

provided on the read port for three-state control of the output.

The synchronous FIFOs have two fixed flags, Empty (

) and

Full (

), and two programmable flags, Almost-Empty (

PAE

)

and Almost-Full (

PAF

). The offset loading of the programmable

flags is controlled by a simple state machine, and is initiated by

asserting the Load pin (

). A Half-Full flag (

) is available

when the FIFO is used in a single device configuration.

These devices are depth expandable using a Daisy-Chain

technique. The XI and

pins are used to expand the FIFOs.

In depth expansion configuration,

is grounded on the first

device and set to HIGH for all other devices in the Daisy Chain.

The IDT72205LB/72215LB/72225LB/72235LB/72245LB is

fabricated using IDT’s high-speed submicron CMOS technol-

ogy.

FUNCTIONAL BLOCK DIAGRAM

WCLK

D0-D17

INPUT REGISTER

OFFSET REGISTER

WRITE CONTROL

LOGIC

WRITE POINTER

•

RAM ARRAY

256 x 18, 512 x 18

1,024 x 18, 2,048 x 18

4,096 x 18

•

FLAG

LOGIC

READ POINTER

READ CONTROL

LOGIC

)

(

EXPANSION LOGIC

OUTPUT REGISTER

RESET LOGIC

Q0-Q17

SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc

RCLK

2766 drw 01

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

MAY 2000

DSC-2766/-

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