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FAN6300 — Highly Integrated Quasi-Resonant Current Mode PWM Controller
October 2008
FAN6300
Highly Integrated Quasi-Resonant Current Mode
PWM Controller
Features
High-Voltage Startup
Quasi-Resonant Operation
Cycle-by-Cycle Current Limiting
Peak-Current-Mode Control
Leading-Edge Blanking
Internal Minimum t
OFF
Internal 2ms Soft-Start
Over-Power Compensation
GATE Output Maximum Voltage
Auto-Recovery Short-Circuit Protection (FB Pin)
Auto-Recovery Open-Loop Protection (FB Pin)
VDD Pin & Output Voltage (DET Pin) OVP Latched
Description
The highly integrated FAN6300 PWM controller
provides several features to enhance the performance
of flyback converters. A built-in HV startup circuit can
provide more startup current to reduce the startup time
of the controller. Once the V
DD
voltage exceeds the
turn-on threshold voltage, the HV startup function is
disabled immediately to improve power consumption.
An internal valley voltage detector ensures the power
system operates at Quasi-Resonant operation in wide-
range line voltage and any load conditions and reduces
switching loss to minimize switching voltage on drain of
power MOSFET.
To minimize standby power consumption and light-load
efficiency, a proprietary green-mode function provides
off-time modulation to decrease switching frequency
and perform extended valley voltage switching to keep
to a minimum switching voltage.
FAN6300 controller also provides many protection
functions. Pulse-by-pulse current limiting ensures the
fixed peak current limit level, even when a short circuit
occurs. Once an open-circuit failure occurs in the
feedback loop, the internal protection circuit disables
PWM output immediately. As long as V
DD
drops below
the turn-off threshold voltage, controller also disables
PWM output. The gate output is clamped at 18V to
protect the power MOS from high gate-source voltage
conditions. The minimum t
OFF
time limit prevents the
system frequency from being too high. If the DET pin
reaches OVP, internal OTP is triggered, and the power
system enters latch-mode until AC power is removed.
FAN6300 controller is available in 8-pin SOP and DIP
packages.
Applications
AC/DC NB Adapters
Open-Frame SMPS
Ordering Information
Part Number
FAN6300SY
FAN6300DY
Operating
Temperature Range
-40 to +105°C
-40 to +105°C
Eco Status
Green
Green
Package
8-Lead, Small Out-line Package
(SOP)
8-Lead, Dual In-line Package
(DIP)
Packing Method
Tape & Reel
Tube
For Fairchild’s definition of “green” Eco Status, please visit:
http://www.fairchildsemi.com/company/green/rohs_green.html.
© 2008 Fairchild Semiconductor Corporation
FAN6300 • Rev. 1.0.3
www.fairchildsemi.com
FAN6300 — Highly Integrated Quasi-Resonant Current Mode PWM Controller
Application Diagram
Figure 1. Typical Application
Internal Block Diagram
HV
8
4.2V
I
HV
27V
OVP
VDD
6
Internal
Bias
Two Steps
UVLO
16V/10V/8V
FB
2
Soft-Start
2ms
2R
Latched
R
500µs
30µs
Timer
55ms
FB OLP
Starter
CS
3
Blanking
Circuit
PWM
Current Limit
I
DET
Latched
t
OFF-MIN
(8µs/38µs)
0.3V
V
DET
V
DET
Latched
2.5V
DET OVP
Valley
Detector
1st
Valley
DRV
S
SET
Q
18V
5
GATE
Over-Power
Compensation
R
CLR
Q
t
OFF-MIN
+9µs
t
OFF
Blanking
(4µs)
S/H
DET
1
5V
I
DET
0.3V
Internal
OTP
Latched
4
GND
7
NC
Figure 2. Functional Block Diagram
© 2008 Fairchild Semiconductor Corporation
FAN6300 • Rev. 1.0.3
www.fairchildsemi.com
2
FAN6300 — Highly Integrated Quasi-Resonant Current Mode PWM Controller
Marking Information
: Fairchild logo
Z:
Plant Code
X:
Year Code
Y:
Week Code
TT:
Die Run Code
T:
Package type (D =DIP, S = SOP)
P:
Y = Green Package
M:
Manufacturing flow code
Figure 3. Marking Diagram
Pin Configuration
Figure 4. Pin Configuration
Pin Definitions
Pin #
Name
Description
This pin is connected to an auxiliary winding of the transformer via resistors of the divider for
the following purposes:
-
Generates a ZCD signal once the secondary-side switching current falls to zero.
-
Produces an offset voltage to compensate the threshold voltage of the peak current limit to
provide a constant power limit. The offset is generated in accordance with the input voltage
when PWM signal is enabled.
-
Detects the valley voltage of the switching waveform to achieve the valley voltage switching
and minimize the switching losses.
A voltage comparator and a 2.5V reference voltage develop an output OVP protection. The
ratio of the divider decides what output voltage to stop gate, as an optical coupler and
secondary shunt regulator are used.
The Feedback pin is supposed to be connected to the output of the error amplifier for achieving
the voltage control loop. The FB should be connected to the output of the optical coupler if the
error-amplifier is equipped at the secondary-side of the power converter.
2
FB
For the primary-side control application, this pin is applied to connect a RC network to the
ground for feedback-loop compensation.
The input impedance of this pin is a 5kΩ equivalent resistance. A 1/3 attenuator connected
between the FB and the PWM circuit is used for the loop gain attenuation.
FAN6300 performs an open-loop protection once the FB voltage is higher than a threshold
voltage (around 4.2V) more than 55ms.
© 2008 Fairchild Semiconductor Corporation
FAN6300 • Rev. 1.0.3
1
DET
www.fairchildsemi.com
3
FAN6300 — Highly Integrated Quasi-Resonant Current Mode PWM Controller
Pin #
3
4
5
6
7
8
Name
CS
GND
GATE
VDD
NC
HV
Description
Input to the comparator of the over-current protection. A resistor senses the switching current
and the resulting voltage is applied to this pin for the cycle-by-cycle current limit. The threshold
voltage for peak current limit is 0.8V.
The power ground and signal ground. A 0.1µF decoupling capacitor placed between V
DD
and
GND is recommended.
Totem-pole output generates the PWM signal to drive the external power MOSFET. The
clamped gate output voltage is 18V.
Power supply. The threshold voltages for startup and turn-off are 16V and 10V. The startup
current is less than 20µA and the operating current is lower than 4.5mA.
No connect.
High-voltage startup.
© 2008 Fairchild Semiconductor Corporation
FAN6300 • Rev. 1.0.3
www.fairchildsemi.com
4
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