C Disclaimer to Page ..................................................... 20
5/03—Revision 0: Initial Version
Rev. B | Page 2 of 20
AD5245
ELECTRICAL CHARACTERISTICS
5 kΩ VERSION
V
DD
= 5 V ± 10% or 3 V ± 10%, V
A
= V
DD
, V
B
= 0 V, –40°C < T
A
< +125°C, unless otherwise noted.
Table 1.
Parameter
Symbol
Conditions
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity
2
R-DNL
R
WB
, V
A
= no connect
2
Resistor Integral Nonlinearity
R-INL
R
WB
, V
A
= no connect
3
Nominal Resistor Tolerance
∆R
AB
T
A
= 25°C
6
Resistance Temperature Coefficient
(∆R
AB
/R
AB
)/∆T × 10
V
AB
= V
DD
, wiper = no connect
Wiper Resistance
R
W
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs)
Differential Nonlinearity
4
DNL
4
Integral Nonlinearity
INL
Voltage Divider Temperature Coefficient
(∆V
W
/V
W
)/∆T × 10
6
Code = 0x80
Full-Scale Error
V
WFSE
Code = 0xFF
Zero-Scale Error
V
WZSE
Code = 0x00
RESISTOR TERMINALS
Voltage Range
5
V
A
, V
B
, V
W
f = 1 MHz, measured to GND,
Capacitance A, B
6
C
A
, C
B
code = 0x80
f = 1 MHz, measured to GND,
Capacitance W
6
C
W
code = 0x80
7
Shutdown Supply Current
I
A_SD
V
DD
= 5.5 V
Common-Mode Leakage
I
CM
V
A
= V
B
= V
DD
/2
DIGITAL INPUTS AND OUTPUTS
Input Logic High
V
IH
V
DD
= 5 V
Input Logic Low
V
IL
V
DD
= 5 V
Input Logic High
V
IH
V
DD
= 3 V
Input Logic Low
V
IL
V
DD
= 3 V
Input Current
I
IL
V
IN
= 0 V or 5 V
6
Input Capacitance
C
IL
POWER SUPPLIES
Power Supply Range
V
DD RANGE
Supply Current
I
DD
V
IH
= 5 V or V
IL
= 0 V
8
Power Dissipation
P
DISS
V
IH
= 5 V or V
IL
= 0 V, V
DD
= 5 V
Power Supply Sensitivity
PSS
V
DD
= +5 V ± 10%, code = midscale
6, 9
DYNAMIC CHARACTERISTICS
Bandwidth –3 dB
BW_5K
R
AB
= 5 kΩ, code = 0x80
Total Harmonic Distortion
THD
W
V
A
= 1 V rms, V
B
= 0 V, f = 1 kHz
V
W
Settling Time
t
S
V
A
= 5 V, V
B
= 0 V, ±1 LSB error band
Resistor Noise Voltage Density
e
N_WB
R
WB
= 2.5 kΩ, R
S
= 0
1
2
Min
–1.5
–4
–30
Typ
1
±0.1
±0.75
45
50
Max
+1.5
+4
+30
120
+1.5
+1.5
0
6
V
DD
Unit
LSB
LSB
%
ppm/°C
Ω
LSB
LSB
ppm/°C
LSB
LSB
V
pF
pF
µA
nA
V
V
V
V
µA
pF
V
µA
µW
%/%
MHz
%
µs
nV/√Hz
–1.5
–1.5
–6
0
GND
±0.1
±0.6
15
–2.5
2
90
95
0.01
1
2.4
0.8
2.1
0.6
±1
5
2.7
3
±0.02
1.2
0.1
1
6
5.5
8
44
±0.05
1
Typical specifications represent average readings at 25°C and V
DD
= 5 V.
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
V
AB
= V
DD
, wiper (V
W
) = no connect.
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor Terminals A, B, and W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Measured at the A terminal. The A terminal is open circuited in shutdown mode.
8
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
9
All dynamic characteristics use V
DD
= 5 V.
Rev. B | Page 3 of 20
AD5245
10 kΩ, 50 kΩ, 100 kΩ VERSIONS
V
DD
= 5 V ± 10% or 3 V ± 10%, V
A
= V
DD
, V
B
= 0 V, –40°C < T
A
< +125°C, unless otherwise noted.
Table 2.
Parameter
Symbol
Conditions
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity
2
R-DNL
R
WB
, V
A
= no connect
Resistor Integral Nonlinearity
2
R-INL
R
WB
, V
A
= no connect
3
Nominal Resistor Tolerance
∆R
AB
T
A
= 25°C
6
Resistance Temperature Coefficient
(∆R
AB
/R
AB
)/∆T × 10
V
AB
= V
DD
, wiper = no connect
Wiper Resistance
R
W
V
DD
= 5 V
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs)
Differential Nonlinearity
4
DNL
4
Integral Nonlinearity
INL
Voltage Divider Temperature Coefficient (∆V
W
/V
W
)/∆T × 10
6
Code = 0x80
Full-Scale Error
V
WFSE
Code = 0xFF
Zero-Scale Error
V
WZSE
Code = 0x00
RESISTOR TERMINALS
Voltage Range
5
V
A
, V
B
, V
W
6
Capacitance A, B
C
A
, C
B
f = 1 MHz, measured to GND,
code = 0x80
6
Capacitance W
C
W
f = 1 MHz, measured to GND,
code = 0x80
Shutdown Supply Current
I
A_SD
V
DD
= 5.5 V
Common-Mode Leakage
I
CM
V
A
= V
B
= V
DD
/2
DIGITAL INPUTS AND OUTPUTS
Input Logic High
V
IH
V
DD
= 5 V
Input Logic Low
V
IL
V
DD
= 5 V
Input Logic High
V
IH
V
DD
= 3 V
Input Logic Low
V
IL
V
DD
= 3 V
Input Current
I
IL
V
IN
= 0 V or 5 V
6
Input Capacitance
C
IL
POWER SUPPLIES
Power Supply Range
V
DD RANGE
Supply Current
I
DD
V
IH
= 5 V or V
IL
= 0 V
7
Power Dissipation
P
DISS
V
IH
= 5 V or V
IL
= 0 V, V
DD
= 5 V
Power Supply Sensitivity
PSS
V
DD
= 5 V ± 10%,
code = midscale
6, 8
DYNAMIC CHARACTERISTICS
Bandwidth –3 dB
BW
R
AB
= 10 kΩ/50 kΩ/100 kΩ,
code = 0x80
Total Harmonic Distortion
THD
W
V
A
= 1 V rms, V
B
= 0 V, f = 1 kHz,
R
AB
= 10 kΩ
V
W
Settling Time (10 kΩ/50 kΩ/100 kΩ)
t
S
V
A
= 5 V, V
B
= 0 V,
±1 LSB error band
Resistor Noise Voltage Density
e
N_WB
R
WB
= 5 kΩ, R
S
= 0
1
2
Min
–1
–2
–30
Typ
1
±0.1
±0.25
45
50
Max
+1
+2
+30
120
+1
+1
0
3
V
DD
Unit
LSB
LSB
%
ppm/°C
Ω
LSB
LSB
ppm/°C
LSB
LSB
V
pF
pF
–1
–1
–3
0
GND
±0.1
±0.3
15
–1
1
90
95
0.01
1
2.4
0.8
2.1
0.6
±1
5
2.7
3
±0.02
5.5
8
44
±0.05
1
µA
nA
V
V
V
V
µA
pF
V
µA
µW
%/%
600/100/40
0.1
2
9
kHz
%
µs
nV/√Hz
Typical specifications represent average readings at 25°C and V
DD
= 5 V.
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
V
AB
= V
DD
, wiper (V
W
) = no connect.
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor Terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
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