EEWORLDEEWORLDEEWORLD

Part Number

Search

UPL40-10

Description
CONNECTOR, CABLE TERMINATED, MALE, TNC CONNECTOR, CRIMP, PLUG
CategoryThe connector    The connector   
File Size60KB,1 Pages
ManufacturerArtysen Embedded Technologies
Download Datasheet Parametric View All

UPL40-10 Overview

CONNECTOR, CABLE TERMINATED, MALE, TNC CONNECTOR, CRIMP, PLUG

UPL40-10 Parametric

Parameter NameAttribute value
MakerArtysen Embedded Technologies
Reach Compliance Codeunknown
ECCN codeEAR99
Other featuresAPPLICABLE CABLE: BELDEN 9231
Body/casing typePLUG
Characteristic impedance75 Ω
Connector typeRF TNC CONNECTOR
Contact to complete cooperationNOT SPECIFIED
Contact point genderMALE
Coupling typeTHREADED
DIN complianceNO
Filter functionNO
IEC complianceNO
Insertion loss1 dB
insulator materialPOLYTETRAFLUORO ETHYLENE
MIL complianceNO
Manufacturer's serial number40
Installation methodSTRAIGHT
Installation typeCABLE
Maximum operating frequency11 GHz
OptionsGENERAL PURPOSE
Panel mountingNO
Termination typeCRIMP
voltage standing wave ratio1.3
28
Miniature coax threaded 40/240 series, tnc
PL40-1 Shown
,,,,,,,
,,,,,,,
,,,,,,,
,,,,,,,
,,,,,,,
,,,,,,,
,,,,,,,
,,,,,,,
,,,,,,,
,,,,,,,
,,,,,,,
.437 OR .500
WRENCH FLATS
AND NUT
CJ40-1 Shown
.997
,,
,,
,,
,,
,,
.437 HEX
.960/1.001
.096
.4375-28UNEF-2A
.645 DIA MAX
.096
Cable Plug
Wrench Crimp
50Ω
75Ω
PL40-
UPL40-
1
1
Cable Jack
Wrench Crimp
50Ω
75Ω
CJ40-
UCJ40-
1
1
1.140
1.208
.708
,,,,,,,
,,,,,,,
,,,,,,,
,,,,,,,
,,,,,,,
,,,,,,,
,,,,,,,
,,,,,,,
,,,,,,,
.650 DIA MAX
.640
.593
DIA
MAX
,,,,
,,,,
,,,,
,,,,
,,,,
,,,,
,,,,
,,,,
,,,,
,,,,
,,,,
.4375-28UNEF-2A
CRIMP SLEEVE
CJ240-001 SHOWN
Cable Plug
Tool Crimp
50Ω
75Ω
PL240-
UPL240-
1
1
Cable Jack
Tool Crimp
50Ω
75Ω
CJ240-
UCJ240-
1
1
.437 WRENCH FLATS
.625 DIA MAX
.500 HEX NUT
.375-32UNEF-2A
SOLDER POT ACCEPTS
.064 DIA CONDUCTOR
1.280
.029 DIA
3 HOLES
.250
.400
1.11
.381
Bulkhead Plug
Front mount, Solder pot
w/ Solder Lug
Mounting Hole:
C2.093
BJ48 Shown
50Ω
75Ω
50Ω
75Ω
PL41
UPL41
PL41SL
UPL41SL
.4375.28UNEF-2A TYP
TNC Coupling Adapter
(Barrel connector)
50Ω
75Ω
AD48
UAD48
C
DIM
.070
.070
.090
.090
D
E
DIM DIM
.050 .0625
.050 .0625
.058 .070
.058 .070
1.282
.505
.046
MODEL
LTR
NO.
CODE OHM
CBJR40
-
50
UCBJR40
-
75
CBJR40A
A
50
UCBJR40A
A
75
A
DIM
.046
.029
.046
.029
B
DIM
.24
.24
.34
.34
1.054
.890
.380
DIA
.030
TYP
B TYP
.500-28UNEF-2A
.562 HEX NUT
.562 HEX
.4375-28UNEF-2A
C TYP
.258
TYP
.13 TYP
D TYP
E TYP
Insulated
Bulkhead Jack
Feed-through
Mounting Hole:
D3.156
GF
-Ground filter version page 31.
1
50Ω
75Ω
BJ48
UBJ48
Right Angle
Circuit Board
Mounting
TNC Receptacle
CBJR40
50Ω
75Ω
UCBJR40
Add "A" for tall versions
(see chart)
.258
.258
A
- Refers to Cable Group Table, see pages 68-88. "D" mounting holes are on page 45.
Trompeter Products Catalog
ISO 9001
Registered
R
(800) 982-2629
Fax: (818) 706-1040
Problems encountered when using DDS
[i=s] This post was last edited by paulhyde on 2014-9-15 09:18 [/i] Please give me some advice. When using DDS, I am using AD9851 and I have encountered this problem: I need to press the reset button ...
fpga126 Electronics Design Contest
DSP2000 assembly language, looking at other people's programs and encountering a difficulty
The difficulty is that I really don't understand what "varStartPtr" does in the program? The following are the places where "varStartPtr" appears in the entire project file. h file: varStartPtr .usect...
独孤求败2030 DSP and ARM Processors
Why do voice chips have malfunctions?
Why do voice chips have malfunctions?...
牟允允 Domestic Chip Exchange
About the capture and timing state conversion of Timer_B7
I use Timer_B7 in MSP430F147 to measure multiple switch quantities. In order to improve the accuracy, I plan to use the capture mode to capture the required transition edge, and then use the module to...
yzg092 Microcontroller MCU
6410 CAMERA
Platform: S3C6410 + WinCE6.0 Symptom: Modified the original CAMERA driver in Samsung official BSP to support OV3640 (3 million pixels) Now preview: 640x480 still: 1024x768 is OK, but when still is set...
yiabc Embedded System
Register put in IOB settings
Example module code: [color=indigo]module design_top(clk, A, B, C, D, E,rst_n); input clk, A, B, rst_n; output reg C, D, E; reg temp_a; reg temp_b; always @(posedge clk or negedge rst_n) begin if (rst...
樱雅月 FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 646  989  349  2515  2096  13  20  8  51  43 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号