Intel
®
Celeron
®
Processor 400
Δ
Series
Datasheet
— Supporting the Intel
®
Celeron
®
processor 420
Δ
, 430
Δ
, 440
Δ
, and
450
Δ
August 2008
Document Number: 316963-002
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS
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TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
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INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Δ
Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different
processor families. See http://www.intel.com/products/processor_number for details. Over time processor numbers will increment based on changes in
clock, speed, cache, FSB, or other features, and increments are not intended to represent proportional or quantitative increases in any particular
feature. Current roadmap processor number progression is not necessarily representative of future roadmaps. See www.intel.com/products/
processor_number for details.
Intel
®
64 requires a computer system with a processor, chipset, BIOS, operating system, device drivers, and applications enabled for Intel 64. Processor
will not operate (including 32-bit operation) without an Intel 64-enabled BIOS. Performance will vary depending on your hardware and software
configurations. See http://www.intel.com/technology/intel64/index.htm for more information including details on which processors support Intel 64, or
consult with your system vendor for more information.
Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check
with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel
®
Celeron
®
processor 400 series may contain design defects or errors known as errata which may cause the product to deviate from published
specifications.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Intel, Celeron, Pentium, Intel Core, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2007–2008 Intel Corporation.
2
Datasheet
Contents
1
Introduction
.............................................................................................................. 9
1.1
Terminology ....................................................................................................... 9
1.1.1 Processor Packaging Terminology ............................................................. 10
1.2
References ....................................................................................................... 11
Electrical Specifications
........................................................................................... 13
2.1
Power and Ground Lands.................................................................................... 13
2.2
Decoupling Guidelines ........................................................................................ 13
2.2.1 Vcc Decoupling ...................................................................................... 13
2.2.2 Vtt Decoupling ....................................................................................... 13
2.2.3 FSB Decoupling...................................................................................... 14
2.3
Voltage Identification ......................................................................................... 14
2.4
Market Segment Identification (MSID) ................................................................. 16
2.5
Reserved, Unused and TESTHI Signals ................................................................. 16
2.6
Voltage and Current Specification ........................................................................ 17
2.6.1 Absolute Maximum and Minimum Ratings .................................................. 17
2.6.2 DC Voltage and Current Specification ........................................................ 19
2.6.3 Vcc Overshoot ....................................................................................... 21
2.6.4 Die Voltage Validation ............................................................................. 22
2.7
Signaling Specifications...................................................................................... 22
2.7.1 FSB Signal Groups.................................................................................. 23
2.7.2 CMOS and Open Drain Signals ................................................................. 25
2.7.3 Processor DC Specifications ..................................................................... 25
2.7.3.1 GTL+ Front Side Bus Specifications ............................................. 27
2.8
Clock Specifications ........................................................................................... 28
2.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking ............................ 28
2.8.2 FSB Frequency Select Signals (BSEL[2:0])................................................. 29
2.8.3 Phase Lock Loop (PLL) and Filter .............................................................. 29
2.8.4 BCLK[1:0] Specifications (CK505 based Platforms) ..................................... 30
2.8.5 BCLK[1:0] Specifications (CK410 based Platforms) ..................................... 32
2.9
PECI DC Specifications ....................................................................................... 34
Package Mechanical Specifications
.......................................................................... 35
3.1
Package Mechanical Drawing............................................................................... 35
3.2
Processor Component Keep-Out Zones ................................................................. 39
3.3
Package Loading Specifications ........................................................................... 39
3.4
Package Handling Guidelines............................................................................... 39
3.5
Package Insertion Specifications.......................................................................... 40
3.6
Processor Mass Specification ............................................................................... 40
3.7
Processor Materials............................................................................................ 40
3.8
Processor Markings............................................................................................ 40
3.9
Processor Land Coordinates ................................................................................ 41
Land Listing and Signal Descriptions
....................................................................... 43
4.1
Processor Land Assignments ............................................................................... 43
4.2
Alphabetical Signals Reference ............................................................................ 66
Thermal Specifications and Design Considerations
.................................................. 75
5.1
Processor Thermal Specifications ......................................................................... 75
5.1.1 Thermal Specifications ............................................................................ 75
5.1.2 Thermal Metrology ................................................................................. 78
5.2
Processor Thermal Features ................................................................................ 78
5.2.1 Thermal Monitor..................................................................................... 78
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3
4
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Datasheet
3
5.3
5.4
5.2.2 Thermal Monitor 2 ..................................................................................79
5.2.3 On-Demand Mode ...................................................................................80
5.2.4 PROCHOT# Signal ..................................................................................81
5.2.5 THERMTRIP# Signal ................................................................................81
Thermal Diode...................................................................................................82
Platform Environment Control Interface (PECI) ......................................................84
5.4.1 Introduction ...........................................................................................84
5.4.1.1 Key Difference with Legacy Diode-Based Thermal Management .......84
5.4.2 PECI Specifications .................................................................................86
5.4.2.1 PECI Device Address..................................................................86
5.4.2.2 PECI Command Support .............................................................86
5.4.2.3 PECI Fault Handling Requirements ...............................................86
5.4.2.4 PECI GetTemp0() Error Code Support ..........................................86
6
Features
..................................................................................................................87
6.1
Power-On Configuration Options ..........................................................................87
6.2
Clock Control and Low Power States .....................................................................87
6.2.1 Normal State .........................................................................................88
6.2.2 HALT and Extended HALT Powerdown States ..............................................88
6.2.2.1 HALT Powerdown State ..............................................................88
6.2.2.2 Extended HALT Powerdown State ................................................89
6.2.3 Stop Grant State ....................................................................................89
6.2.4 HALT Snoop State and Stop Grant Snoop State...........................................90
Boxed Processor Specifications................................................................................91
7.1
Mechanical Specifications ....................................................................................92
7.1.1 Boxed Processor Cooling Solution Dimensions.............................................92
7.1.2 Boxed Processor Fan Heatsink Weight .......................................................94
7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly .....94
7.2
Electrical Requirements ......................................................................................94
7.2.1 Fan Heatsink Power Supply ......................................................................94
7.3
Thermal Specifications........................................................................................95
7.3.1 Boxed Processor Cooling Requirements......................................................95
7.3.2 Variable Speed Fan .................................................................................97
Debug Tools Specifications
......................................................................................99
8.1
Logic Analyzer Interface (LAI) .............................................................................99
8.1.1 Mechanical Considerations .......................................................................99
8.1.2 Electrical Considerations ..........................................................................99
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Datasheet
Figures
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25
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27
28
29
30
31
V
CC
Static and Transient Tolerance ............................................................................. 21
V
CC
Overshoot Example Waveform ............................................................................. 22
Differential Clock Waveform ...................................................................................... 30
Differential Clock Crosspoint Specification ................................................................... 31
Differential Measurements......................................................................................... 31
Differential Clock Waveform ...................................................................................... 33
Differential Clock Crosspoint Specification ................................................................... 33
Processor Package Assembly Sketch ........................................................................... 35
Processor Package Drawing Sheet 1 of 3 ..................................................................... 36
Processor Package Drawing Sheet 2 of 3 ..................................................................... 37
Processor Package Drawing Sheet 3 of 3 ..................................................................... 38
Processor Top-Side Marking Example .......................................................................... 40
Processor Land Coordinates and Quadrants, Top View ................................................... 41
land-out Diagram (Top View – Left Side) ..................................................................... 44
land-out Diagram (Top View – Right Side) ................................................................... 45
Thermal Profile ........................................................................................................ 77
Case Temperature (TC) Measurement Location ............................................................ 78
Thermal Monitor 2 Frequency and Voltage Ordering ...................................................... 80
Processor PECI Topology ........................................................................................... 84
Conceptual Fan Control on PECI-Based Platforms ......................................................... 85
Conceptual Fan Control on Thermal Diode-Based Platforms............................................ 85
Processor Low Power State Machine ........................................................................... 88
Mechanical Representation of the Boxed Processor ....................................................... 91
Space Requirements for the Boxed Processor (Side View).............................................. 92
Space Requirements for the Boxed Processor (Top View)............................................... 93
Space Requirements for the Boxed Processor (Overall View) .......................................... 93
Boxed Processor Fan Heatsink Power Cable Connector Description .................................. 94
Baseboard Power Header Placement Relative to Processor Socket ................................... 95
Boxed Processor Fan Heatsink Airspace Keepout Requirements (Top 1 view) .................... 96
Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 2 View)................... 96
Boxed Processor Fan Heatsink Set Points..................................................................... 97
Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
References .............................................................................................................. 11
Voltage Identification Definition ................................................................................. 15
Market Segment Selection Truth Table for MSID[1:0] ................................................... 16
Absolute Maximum and Minimum Ratings .................................................................... 18
Voltage and Current Specifications ............................................................................. 19
V
CC
Static and Transient Tolerance ............................................................................. 20
V
CC
Overshoot Specifications ..................................................................................... 21
FSB Signal Groups ................................................................................................... 23
Signal Characteristics ............................................................................................... 24
Signal Reference Voltages ......................................................................................... 24
GTL+ Signal Group DC Specifications.......................................................................... 25
Open Drain and TAP Output Signal Group DC Specifications ........................................... 25
CMOS Signal Group DC Specifications ......................................................................... 26
GTL+ Bus Voltage Definitions .................................................................................... 27
Core Frequency to FSB Multiplier Configuration ............................................................ 28
BSEL[2:0] Frequency Table for BCLK[1:0] ................................................................... 29
Front Side Bus Differential BCLK Specifications............................................................. 30
Front Side Bus Differential BCLK Specifications............................................................. 32
PECI DC Electrical Limits ........................................................................................... 34
Processor Loading Specifications ................................................................................ 39
Datasheet
5
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