Intel
®
I/O Controller Hub 10
(ICH10) Family
Datasheet
October 2008
Document Number: 319973-003
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®
I/O Controller Hub 10 (ICH10) Family chipset component may contain design defects or errors known as errata which may cause the product
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Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
I
2
C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I
2
C bus/protocol and was developed by Intel.
Implementations of the I
2
C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips
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®
Active Management Technology requires the computer system to have an Intel
®
AMT-enabled chipset, network hardware and software, as well as
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®
Virtualization Technology requires a computer system with an enabled Intel
®
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®
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®
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®
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®
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®
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®
High Definition Audio requires a system with an appropriate Intel chipset and a motherboard with an appropriate codec and the necessary drivers
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Copyright © 2008, Intel Corporation
2
Datasheet
Contents
1
Introduction
............................................................................................................ 33
1.1
About This Manual ............................................................................................. 33
1.2
Overview ......................................................................................................... 37
1.2.1 Capability Overview ................................................................................ 39
1.3
Intel
®
ICH10 Family High-Level Component Differences ......................................... 44
Signal Description
................................................................................................... 45
2.1
Direct Media Interface (DMI) to Host Controller ..................................................... 47
2.2
PCI Express* Interface....................................................................................... 48
2.3
LAN Connect Interface ....................................................................................... 48
2.4
Gigabit LAN Connect Interface ............................................................................ 49
2.5
Firmware Hub Interface...................................................................................... 50
2.6
PCI Interface .................................................................................................... 50
2.7
Serial ATA Interface........................................................................................... 52
2.8
LPC Interface.................................................................................................... 55
2.9
Interrupt Interface ............................................................................................ 55
2.10 USB Interface ................................................................................................... 56
2.11 Power Management Interface.............................................................................. 58
2.12 Processor Interface............................................................................................ 61
2.13 SMBus Interface................................................................................................ 62
2.14 System Management Interface............................................................................ 63
2.15 Real Time Clock Interface ................................................................................... 64
2.16 Other Clocks..................................................................................................... 65
2.17 Miscellaneous Signals ........................................................................................ 65
2.18 Intel
®
High Definition Audio Link ......................................................................... 66
2.19 Serial Peripheral Interface (SPI) .......................................................................... 67
2.20 Controller Link .................................................................................................. 68
2.21 Intel
®
Quiet System Technology ......................................................................... 68
2.22 JTAG Signals (Intel
®
ICH10 Corporate Family Only) ............................................... 69
2.23 General Purpose I/O Signals ............................................................................... 70
2.24 Power and Ground Signals .................................................................................. 73
2.25 Pin Straps ........................................................................................................ 75
2.25.1 Functional Straps ................................................................................... 75
2.25.2 External RTC Circuitry ............................................................................. 79
Intel
®
ICH10 Pin States...........................................................................................
81
3.1
Integrated Pull-Ups and Pull-Downs ..................................................................... 81
3.2
Output and I/O Signals Planes and States............................................................. 83
3.3
Power Planes for Input Signals ............................................................................ 88
Intel
®
ICH10 and System Clock Domains.................................................................
91
Functional Description
............................................................................................. 93
5.1
DMI-to-PCI Bridge (D30:F0) ............................................................................... 93
5.1.1 PCI Bus Interface ................................................................................... 93
5.1.2 PCI Bridge As an Initiator ........................................................................ 93
5.1.3 Parity Error Detection and Generation ....................................................... 95
5.1.4 PCIRST# ............................................................................................... 96
5.1.5 Peer Cycles ........................................................................................... 96
5.1.6 PCI-to-PCI Bridge Model.......................................................................... 96
5.1.7 IDSEL to Device Number Mapping ............................................................ 97
5.1.8 Standard PCI Bus Configuration Mechanism ............................................... 97
5.2
PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5).................................................. 97
5.2.1 Interrupt Generation............................................................................... 97
5.2.2 Power Management ................................................................................ 98
5.2.3 SERR# Generation ................................................................................. 99
5.2.4 Hot-Plug ............................................................................................. 100
5.3
Gigabit Ethernet Controller (B0:D25:F0)............................................................. 101
5.3.1 Gigabit Ethernet PCI Bus Interface.......................................................... 102
5.3.2 Error Events and Error Reporting ............................................................ 103
5.3.3 Ethernet Interface ................................................................................ 103
5.3.4 PCI Power Management ........................................................................ 104
5.3.5 Configurable LEDs ................................................................................ 105
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5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
5.13
5.14
5.15
5.3.6 Function Level Reset Support (FLR) ......................................................... 106
LPC Bridge (w/ System and Management Functions) (D31:F0) ............................... 107
5.4.1 LPC Interface ....................................................................................... 107
DMA Operation (D31:F0) .................................................................................. 112
5.5.1 Channel Priority.................................................................................... 113
5.5.2 Address Compatibility Mode ................................................................... 113
5.5.3 Summary of DMA Transfer Sizes ............................................................. 114
5.5.4 Autoinitialize ........................................................................................ 114
5.5.5 Software Commands ............................................................................. 115
LPC DMA ........................................................................................................ 115
5.6.1 Asserting DMA Requests ........................................................................ 115
5.6.2 Abandoning DMA Requests..................................................................... 116
5.6.3 General Flow of DMA Transfers ............................................................... 116
5.6.4 Terminal Count..................................................................................... 116
5.6.5 Verify Mode ......................................................................................... 117
5.6.6 DMA Request Deassertion ...................................................................... 117
5.6.7 SYNC Field / LDRQ# Rules ..................................................................... 118
8254 Timers (D31:F0) ...................................................................................... 118
5.7.1 Timer Programming .............................................................................. 119
5.7.2 Reading from the Interval Timer ............................................................. 120
8259 Interrupt Controllers (PIC) (D31:F0)........................................................... 121
5.8.1 Interrupt Handling ................................................................................ 122
5.8.2 Initialization Command Words (ICWx) ..................................................... 123
5.8.3 Operation Command Words (OCW) ......................................................... 124
5.8.4 Modes of Operation ............................................................................... 124
5.8.5 Masking Interrupts................................................................................ 127
5.8.6 Steering PCI Interrupts.......................................................................... 127
Advanced Programmable Interrupt Controller (APIC) (D31:F0)............................... 128
5.9.1 Interrupt Handling ................................................................................ 128
5.9.2 Interrupt Mapping................................................................................. 128
5.9.3 PCI / PCI Express* Message-Based Interrupts .......................................... 129
5.9.4 Front Side Bus Interrupt Delivery ............................................................ 129
5.9.5 IOxAPIC Address Remapping .................................................................. 131
5.9.6 External Interrupt Controller Support ...................................................... 131
Serial Interrupt (D31:F0) .................................................................................. 132
5.10.1 Start Frame ......................................................................................... 132
5.10.2 Data Frames ........................................................................................ 133
5.10.3 Stop Frame.......................................................................................... 133
5.10.4 Specific Interrupts Not Supported via SERIRQ........................................... 133
5.10.5 Data Frame Format............................................................................... 134
Real Time Clock (D31:F0) ................................................................................. 135
5.11.1 Update Cycles ...................................................................................... 135
5.11.2 Interrupts ............................................................................................ 136
5.11.3 Lockable RAM Ranges............................................................................ 136
5.11.4 Century Rollover................................................................................... 136
5.11.5 Clearing Battery-Backed RTC RAM........................................................... 136
Processor Interface (D31:F0) ............................................................................ 138
5.12.1 Processor Interface Signals .................................................................... 138
5.12.2 Dual-Processor Issues ........................................................................... 141
Power Management (D31:F0) ............................................................................ 142
5.13.1 Features .............................................................................................. 142
5.13.2 Intel
®
ICH10 and System Power States ................................................... 142
5.13.3 System Power Planes ............................................................................ 145
5.13.4 SMI#/SCI Generation ............................................................................ 145
5.13.5 Dynamic Processor Clock Control ............................................................ 148
5.13.6 Sleep States ........................................................................................ 151
5.13.7 Thermal Management............................................................................ 154
5.13.8 Event Input Signals and Their Usage ....................................................... 155
5.13.9 ALT Access Mode .................................................................................. 158
5.13.10System Power Supplies, Planes, and Signals............................................. 162
5.13.11Clock Generators .................................................................................. 164
5.13.12Legacy Power Management Theory of Operation ....................................... 165
5.13.13Reset Behavior ..................................................................................... 165
System Management (D31:F0) .......................................................................... 167
5.14.1 Theory of Operation .............................................................................. 167
5.14.2 TCO Modes .......................................................................................... 169
General Purpose I/O (D31:F0) ........................................................................... 173
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5.16
5.17
5.18
5.19
5.20
5.21
5.22
5.23
5.15.1 Power Wells......................................................................................... 173
5.15.2 SMI# and SCI Routing .......................................................................... 173
5.15.3 Triggering ........................................................................................... 173
5.15.4 GPIO Registers Lockdown ...................................................................... 173
5.15.5 Serial POST Codes Over GPIO ................................................................ 174
5.15.6 Intel Management Engine GPIOs ............................................................ 176
SATA Host Controller (D31:F2, F5) .................................................................... 176
5.16.1 SATA Feature Support........................................................................... 177
5.16.2 Theory of Operation.............................................................................. 178
5.16.3 SATA Swap Bay Support ....................................................................... 178
5.16.4 Hot Plug Operation ............................................................................... 178
5.16.5 Function Level Reset Support (FLR) ........................................................ 179
5.16.6 Intel
®
Matrix Storage Technology Configuration ....................................... 180
5.16.7 Power Management Operation................................................................ 181
5.16.8 SATA Device Presence........................................................................... 183
5.16.9 SATA LED............................................................................................ 184
5.16.10AHCI Operation.................................................................................... 184
5.16.11Serial ATA Reference Clock Low Power Request (SATACLKREQ#) ................ 184
5.16.12SGPIO Signals ..................................................................................... 185
5.16.13External SATA...................................................................................... 189
High Precision Event Timers.............................................................................. 189
5.17.1 Timer Accuracy .................................................................................... 189
5.17.2 Interrupt Mapping ................................................................................ 190
5.17.3 Periodic vs. Non-Periodic Modes ............................................................. 190
5.17.4 Enabling the Timers.............................................................................. 191
5.17.5 Interrupt Levels ................................................................................... 191
5.17.6 Handling Interrupts .............................................................................. 192
5.17.7 Issues Related to 64-Bit Timers with 32-Bit Processors .............................. 192
USB UHCI Host Controllers (D29:F0, F1, F2, F3 and D26:F0, F1 and F2) ................. 192
5.18.1 Data Structures in Main Memory............................................................. 193
5.18.2 Data Transfers to/from Main Memory ...................................................... 193
5.18.3 Data Encoding and Bit Stuffing ............................................................... 193
5.18.4 Bus Protocol ........................................................................................ 193
5.18.5 Packet Formats .................................................................................... 194
5.18.6 USB Interrupts..................................................................................... 194
5.18.7 USB Power Management ....................................................................... 197
5.18.8 USB Legacy Keyboard Operation ............................................................ 197
5.18.9 Function Level Reset Support (FLR) ........................................................ 200
USB EHCI Host Controllers (D29:F7 and D26:F7)................................................. 201
5.19.1 EHC Initialization.................................................................................. 201
5.19.2 Data Structures in Main Memory............................................................. 202
5.19.3 USB 2.0 Enhanced Host Controller DMA................................................... 202
5.19.4 Data Encoding and Bit Stuffing ............................................................... 202
5.19.5 Packet Formats .................................................................................... 203
5.19.6 USB 2.0 Interrupts and Error Conditions .................................................. 203
5.19.7 USB 2.0 Power Management .................................................................. 204
5.19.8 Interaction with UHCI Host Controllers .................................................... 205
5.19.9 USB 2.0 Legacy Keyboard Operation ....................................................... 208
5.19.10USB 2.0 Based Debug Port .................................................................... 209
5.19.11USB Pre-Fetch Based Pause ................................................................... 213
5.19.12Function Level Reset Support (FLR) ........................................................ 214
SMBus Controller (D31:F3) ............................................................................... 214
5.20.1 Host Controller..................................................................................... 215
5.20.2 Bus Arbitration..................................................................................... 219
5.20.3 Bus Timing .......................................................................................... 220
5.20.4 Interrupts / SMI#................................................................................. 221
5.20.5 SMBALERT# ........................................................................................ 222
5.20.6 SMBus CRC Generation and Checking...................................................... 222
5.20.7 SMBus Slave Interface .......................................................................... 222
Intel
®
High Definition Audio Overview ................................................................ 228
Intel
®
Active Management Technology (Intel
®
AMT) (Corporate Only).................... 228
5.22.1 Intel
®
AMT Features ............................................................................. 229
5.22.2 Intel
®
AMT Requirements ...................................................................... 229
Serial Peripheral Interface (SPI) ........................................................................ 229
5.23.1 SPI Supported Feature Overview ............................................................ 230
5.23.2 Flash Descriptor ................................................................................... 232
5.23.3 Flash Access ........................................................................................ 234
Datasheet
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