Intel® System Controller Hub
(Intel® SCH)
Datasheet
May 2010
Document Number: 319537-003US
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information here is subject to change without notice. Do not finalize a design with this information.
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without notice. Do not finalize a design with this information.
Intel® High Definition Audio (Intel® HD Audio) requires a system with an appropriate Intel chipset and a motherboard with an
appropriate codec and the necessary drivers installed. System sound quality will vary depending on actual implementation,
controller, codec, drivers and speakers. For more information about Intel® High Definition Audio (Intel® HD Audio), refer to
http://www.intel.com/.
I
2
C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I
2
C bus/protocol and was developed
by Intel. Implementations of the I
2
C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and
North American Philips Corporation.
Intel, Intel® Graphics Media Accelerator 500 (Intel® GMA 500)
,
Intel® High Definition Audio (Intel® HD Audio),
Enhanced Intel SpeedStep® Technology, Intel® Atom
TM
, and the Intel logo are trademarks of Intel Corporation in the U.S. and
other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2008–2010, Intel Corporation. All Rights Reserved.
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Datasheet
Contents
1
Introduction
............................................................................................................ 19
1.1
Terminology ..................................................................................................... 20
1.2
Reference Documents ........................................................................................ 22
1.3
Overview ......................................................................................................... 23
1.3.1 Processor Interface................................................................................. 23
1.3.2 System Memory Controller ...................................................................... 24
1.3.3 USB Host .............................................................................................. 24
1.3.4 USB Client............................................................................................. 24
1.3.5 PCI Express* ......................................................................................... 24
1.3.6 LPC Interface......................................................................................... 24
1.3.7 Parallel ATA (PATA) ................................................................................ 25
1.3.8 Intel® Graphics Media Accelerator 500 (Intel® GMA 500) ........................... 25
1.3.9 Display Interfaces .................................................................................. 25
1.3.10 Secure Digital I/O (SDIO)/Multimedia Card (MMC) Controller ....................... 26
1.3.11 SMBus Host Controller ............................................................................ 26
1.3.12 Intel® High Definition Audio (Intel® HD Audio) Controller ........................... 26
1.3.13 General Purpose I/O (GPIO)..................................................................... 26
1.3.14 Power Management ................................................................................ 26
Signal Description
................................................................................................... 27
2.1
Host Interface Signals........................................................................................ 29
2.2
System Memory Signals ..................................................................................... 32
2.3
Integrated Display Interfaces .............................................................................. 34
2.3.1 LVDS Signals ......................................................................................... 34
2.3.2 Serial Digital Video Output (SDVO) Signals ................................................ 34
2.3.3 Display Data Channel (DDC) and GMBus Support........................................ 35
2.4
Universal Serial Bus (USB) Signals....................................................................... 36
2.5
PCI Express* Signals ......................................................................................... 36
2.6
Secure Digital I/O (SDIO)/MultiMedia Card (MMC) Signals ...................................... 37
2.7
Parallel ATA (PATA) Signals ................................................................................ 38
2.8
Intel HD Audio Interface..................................................................................... 39
2.9
LPC Interface.................................................................................................... 40
2.10 SMBus Interface................................................................................................ 40
2.11 Power Management Interface.............................................................................. 41
2.12 Real Time Clock Interface ................................................................................... 42
2.13 JTAG Interface .................................................................................................. 43
2.14 Miscellaneous Signals and Clocks......................................................................... 43
2.15 General Purpose I/O .......................................................................................... 44
2.16 Power and Ground Signals .................................................................................. 45
2.17 Functional Straps .............................................................................................. 46
Pin States
................................................................................................................ 47
3.1
Pin Reset States................................................................................................ 47
3.2
Integrated Termination Resistors......................................................................... 53
System Clock Domains.............................................................................................
55
Register and Memory Mapping.................................................................................
57
5.1
Intel® SCH Register Introduction ........................................................................ 58
5.2
PCI Configuration Map ....................................................................................... 59
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3
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Datasheet
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5.3
5.4
5.5
System Memory Map..........................................................................................60
5.3.1 Legacy Video Area (A0000h – BFFFFh).......................................................62
5.3.2 Expansion Area (C0000h – DFFFFh) ..........................................................62
5.3.3 Extended System BIOS Area (E0000h – EFFFFh) .........................................62
5.3.4 System BIOS Area (F0000h – FFFFFh) .......................................................62
5.3.5 EHCI Controller Area ...............................................................................62
5.3.6 Programmable Attribute Map (PAM)...........................................................62
5.3.7 Top of Memory Segment (TSEG) ...............................................................63
5.3.8 APIC Configuration Space (FEC00000h – FECFFFFFh)...................................63
5.3.9 High BIOS Area ......................................................................................63
5.3.10 Boot Block Update ..................................................................................63
5.3.11 Memory Shadowing.................................................................................64
5.3.12 Locked Transactions................................................................................64
I/O Address Space .............................................................................................65
5.4.1 Fixed I/O Decode Ranges.........................................................................65
5.4.2 Variable I/O Decode Ranges .....................................................................66
I/O Mapped Registers.........................................................................................67
5.5.1 NSC—NMI Status and Control Register ......................................................67
5.5.2 NMIE—NMI Enable Register......................................................................67
5.5.3 CONFIG_ADDRESS—Configuration Address Register ....................................68
5.5.4 RSTC—Reset Control Register...................................................................69
5.5.5 CONFIG_DATA—Configuration Data Register ..............................................69
6
General Chipset Configuration..................................................................................71
6.1
Root Complex Capability .....................................................................................71
6.1.1 RCTCL—Root Complex Topology Capabilities List.........................................72
6.1.2 ESD—Element Self Description .................................................................72
6.1.3 HDD—Intel® HD Audio Description ...........................................................73
6.1.4 HDBA—Intel® HD Audio Base Address.......................................................73
6.2
Interrupt Pin and Routing Configuration ................................................................74
6.2.1 Interrupt Pin Configuration.......................................................................74
6.2.2 Interrupt Route Configuration...................................................................77
6.3
General Configuration Register ............................................................................80
6.3.1 RC—RTC Configuration Register ................................................................80
Host Bridge (D0:F0)
.................................................................................................81
7.1
Functional Description ........................................................................................81
7.1.1 Dynamic Bus Inversion ............................................................................81
7.1.2 FSB Interrupt Overview ...........................................................................81
7.1.3 CPU BIST Strap ......................................................................................82
7.2
Host PCI Configuration Registers..........................................................................82
7.2.1 VID—Identification Register .....................................................................82
7.2.2 DID—Identification Register .....................................................................83
7.2.3 PCICMD—PCI Command Register ..............................................................83
7.2.4 PCISTS—PCI Status Register ....................................................................83
7.2.5 RID—Revision Identification Register .........................................................83
7.2.6 CC—Class Code Register..........................................................................84
7.2.7 SS—Subsystem Identifiers Register...........................................................84
7.2.8 Miscellaneous (Port 05h)..........................................................................88
Memory Controller (D0:F0)
......................................................................................89
8.1
Functional Overview ...........................................................................................89
8.1.1 DRAM Frequencies and Data Rates ............................................................89
8.1.2 DRAM Command Scheduling ....................................................................89
8.1.3 Page Management ..................................................................................89
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Datasheet
8.2
8.3
8.4
8.5
DRAM Technologies and Organization................................................................... 90
8.2.1 DRAM Address Mapping........................................................................... 90
DRAM Clock Generation...................................................................................... 92
DDR2 On-Die Termination .................................................................................. 92
DRAM Power Management .................................................................................. 92
8.5.1 CKE Powerdown ..................................................................................... 92
8.5.2 Interface High-Impedance ....................................................................... 92
8.5.3 Refresh ................................................................................................. 93
8.5.4 Self-Refresh .......................................................................................... 93
8.5.5 Dynamic Self-Refresh ............................................................................. 93
8.5.6 DDR2 Voltage ........................................................................................ 93
9
Graphics, Video, and Display (D2:F0)
...................................................................... 95
9.1
Graphics Overview ............................................................................................ 95
9.1.1 3-D Core Key Features ............................................................................ 95
9.1.2 Shading Engine Key Features ................................................................... 95
9.1.3 Vertex Processing................................................................................... 96
9.1.4 Pixel Processing ..................................................................................... 97
9.1.5 Unified Shader ....................................................................................... 97
9.1.6 Multi Level Cache ................................................................................... 98
9.2
Video Decode Overview...................................................................................... 98
9.2.1 Entropy Coding ...................................................................................... 99
9.2.2 Motion Compensation ............................................................................. 99
9.2.3 Deblocking .......................................................................................... 100
9.2.4 Output Reference Frame Storage Format ................................................. 100
9.3
Display Overview ............................................................................................ 101
9.3.1 Planes ................................................................................................ 101
9.3.2 Display Pipes ....................................................................................... 102
9.3.3 Display Ports ....................................................................................... 102
9.4
Configuration Registers .................................................................................... 104
9.4.1 VID—Vendor Identification Register ........................................................ 105
9.4.2 DID—Device Identification Register......................................................... 105
9.4.3 PCICMD—PCI Command Register ........................................................... 105
9.4.4 PCISTS—PCI Status Register.................................................................. 106
9.4.5 RID—Revision Identification ................................................................... 106
9.4.6 CC—Class Codes Register ...................................................................... 106
9.4.7 HEADTYP—Header Type Register ............................................................ 107
9.4.8 MEM_BASE—Memory Mapped Base Address Register ................................ 107
9.4.9 IO_BASE—I/O Base Address Register...................................................... 107
9.4.10 GMEM_BASE—Graphics Memory Base Address Register ............................. 108
9.4.11 GTT_BASE—Graphics Translation Table Base Address Register ................... 108
9.4.12 SS—Subsystem Identifiers..................................................................... 109
9.4.13 CAP_PTR—Capabilities Pointer Register ................................................... 109
9.4.14 INT_LN—Interrupt Line Register ............................................................. 109
9.4.15 INT_PN—Interrupt Pin Register .............................................................. 109
9.4.16 GC—Graphics Control Register ............................................................... 110
9.4.17 SSRW—Software Scratch Read/Write Register.......................................... 110
9.4.18 BSM—Base of Stolen Memory Register .................................................... 111
9.4.19 MSAC—Multi Size Aperture Control ......................................................... 111
9.4.20 MSI_CAPID—MSI Capability Register....................................................... 112
9.4.21 NXT_PTR3—Next Item Pointer #3 Register .............................................. 112
9.4.22 MSI_CTL—Message Control Register ....................................................... 112
9.4.23 MSI_ADR—Message Address Register ..................................................... 113
9.4.24 MSI_DATA—Message Data Register ........................................................ 113
9.4.25 VEND_CAPID—Vendor Capability Register................................................ 113
Datasheet
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Microcontroller MCU
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