A
PPLICATION
N
OTES
A V A I L A B L E
AN99 • AN115 • AN120 • AN124 • AN133 • AN134 • AN135
Low Noise/Low Power/2-Wire Bus/256 Taps
X9258
Quad Digital Controlled Potentiometers (XDCP
™
)
FEATURES
•
•
•
•
•
•
•
•
Four potentiometers in one package
256 resistor taps/pot–0.4% resolution
2-wire serial interface
Wiper resistance, 40
Ω
typical @ V+ = 5V, V- = -5V
Four nonvolatile data registers for each pot
Nonvolatile storage of wiper position
Standby current < 5µA max (total package)
Power supplies
—V
CC
= 2.7V to 5.5V
—V+ = 2.7V to 5.5V
—V- = -2.7V to -5.5V
100K
Ω
, 50K
Ω
total pot resistance
High reliability
—Endurance – 100,000 data changes per bit per
register
—Register data retention – 100 years
24-lead SOIC, 24-lead TSSOP, 24-lead CSP (Chip
Scale Package)
Dual supply version of X9259
DESCRIPTION
The X9258 integrates 4 digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated circuit.
The digitally controlled potentiometer is implemented
using 255 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
2-wire bus interface. Each potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and 4 nonvolatile Data Registers (DR0:DR3)
that can be directly written to and read by the user.
The contents of the WCR controls the position of the
wiper on the resistor array though the switches. Power
up recalls the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
•
•
•
•
BLOCK DIAGRAM
V
CC
V
SS
V+
V-
WP
SCL
SDA
A0
A1
A2
A3
R
2
R
3
Pot 0
R
0
R
1
Wiper
Counter
Register
(WCR)
V
H0
/R
H0
R
0
R
1
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 2
V
H2
/R
H2
V
L0
/R
L0
V
W0
/R
W0
R
2
R
3
V
L2
/R
L2
V
W2
/R
W2
Interface
and
Control
Circuitry
8
Data
R
0
R
1
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 1
V
W1
/R
W1
V
H1
/R
H1
R
0
R
1
Wiper
Counter
Register
(WCR)
V
W3
/R
W3
Resistor
Array
Pot 3
V
H3
/R
H3
R
2
R
3
V
L1
/R
L1
R
2
R
3
V
L3
/R
L3
REV 1.1.7 2/4/03
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Characteristics subject to change without notice.
1 of 22
X9258
PIN DESCRIPTIONS
Host Interface Pins
S
ERIAL
C
LOCK
(SCL)
The SCL input is used to clock data into and out of the
X9258.
S
ERIAL
D
ATA
(SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical
values, refer to the guidelines for calculating typical
values on the bus pull-up resistors graph.
D
EVICE
A
DDRESS
(A
0
–
A
3
)
The Address inputs are used to set the least
significant 4 bits of the 8-bit slave address. A match in
the slave address serial data stream must be made
with the address input in order to initiate
communication with the X9258. A maximum of 16
devices may occupy the 2-wire serial bus.
Potentiometer Pins
V
H
/R
H
(V
H0
/R
H0
–V
H3
/R
H3
), V
L
/R
L
(V
L0
/R
L0
–V
L3
/R
L3
)
The V
H
/R
H
and V
L
/R
L
inputs are equivalent to the
terminal connections on either end of a mechanical
potentiometer.
V
W
/R
W
(V
W0
/R
W0
–V
W3
/R
W3
)
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
C
V+
D
R
L3
E
R
W3
F
Top View–Bumps Down
A
0
SCL
R
L2
NC
A
3
R
W2
R
H3
R
H2
V-
1
R
W0
2
A
2
WP
NC
A0
V
W3
/R
W3
V
H3
/R
H3
V
L3
/R
L3
V+
V
CC
V
L0
/R
L0
V
H0
/R
H0
V
W0
/R
W0
A2
WP
PIN CONFIGURATION
SOIC/TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
X9258
24
23
22
21
20
19
18
17
16
15
14
13
A3
SCL
V
L2
/R
L2
V
H2
/R
H2
V
W2
/R
W2
V–
V
SS
V
W1
/R
W1
V
H1
/R
H1
V
L1
/R
L1
A1
SDA
CSP
3
A
1
4
R
L1
R
W1
A
R
L0
B
V
CC
SDA
R
H0
R
H1
V
SS
Hardware Write Protect Input (WP)
The WP pin when low prevents nonvolatile writes to
the Data Registers.
Analog Supplies V+, V-
The Analog Supplies V+, V- are the supply voltages
for the DCP analog section.
REV 1.1.7 2/4/03
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Characteristics subject to change without notice.
2 of 22
X9258
PIN NAMES
Symbol
SCL
SDA
A0-A3
V
H0
/R
H0
–V
H3
/R
H3
,
V
L0
/R
L0
–V
L3
/R
L3
V
W0
/R
W0
–V
W3
/R
W3
WP
V+,V-
V
CC
V
SS
NC
Description
Serial Clock
Serial Data
Device Address
Potentiometer Pins
(terminal equivalent)
Potentiometers Pins
(wiper equivalent)
Hardware Write Protection
Analog Supplies
System Supply Voltage
System Ground
No Connection (Allowed)
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH.
Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data.
The X9258 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9258 will respond with a final acknowledge.
Array Description
The X9258 is comprised of four resistor arrays. Each
array contains 255 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (V
H
/R
H
and V
L
/R
L
inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(V
W
) output. Within each individual array only one
switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
8 bits of the WCR are decoded to select, and enable,
one of 256 switches.
The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
data registers into the WCR. These data registers and
the WCR can be read and written by the host system.
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most
significant four bits of the slave address are the device
type identifier (refer to Figure 1 below). For the X9258
this is fixed as 0101[B].
PRINCIPLES OF OPERATION
The X9258 is a highly integrated microcircuit
incorporating four resistor arrays and their associated
registers and counters and the serial interface logic
providing direct communication between the host and
the DCP potentiometers.
Serial Interface—2-Wire
The X9258 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9258 will be considered a
slave device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods (t
LOW
). SDA state changes during
SCL HIGH are reserved for indicating start and stop
conditions.
Start Condition
All commands to the X9258 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (t
HIGH
). The X9258 continuously
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this
condition is met.
REV 1.1.7 2/4/03
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Characteristics subject to change without notice.
3 of 22
X9258
Figure 1. Slave Address
Device Type
Identifier
ACK Polling Sequence
Nonvolatile Write
Command Completed
EnterACK Polling
0
1
0
1
A3
A2
A1
A0
Issue
START
Device Address
The next four bits of the slave address are the device
address. The physical device address is defined by the
state of the A0-A3 inputs. The X9258 compares the
serial data stream with the address input state; a
successful compare of all four address bits is required
for the X9258 to respond with an acknowledge. The
A
0
–A
3
inputs can be actively driven by CMOS input
signals or tied to V
CC
or V
SS
.
Acknowledge Polling
The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms nonvolatile write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9258
initiates the internal write cycle. ACK polling can be
initiated immediately. This involves issuing the start
condition followed by the device slave address. If the
X9258 is still busy with the write operation no ACK will
be returned. If the X9258 has completed the write
operation an ACK will be returned and the master can
then proceed with the next operation.
Issue Slave
Address
Issue STOP
ACK
Returned?
Yes
Further
Operation?
No
No
Yes
Issue
Instruction
Issue STOP
Proceed
Proceed
Instruction Structure
The next byte sent to the X9258 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next four
bits point to one of the two pots and when applicable
they point to one of four associated registers. The
format is shown below in Figure 2.
REV 1.1.7 2/4/03
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Characteristics subject to change without notice.
4 of 22
X9258
Figure 2. Instruction Byte Format
Register
Select
I3
I2
I1
I0
R1
R0
P1
P0
Instructions
Wiper Counter
Register Select
RAM. The response of the wiper to this action will be
delayed t
WRL
. A transfer from the Wiper Counter
Register (current wiper position), to a data register is a
write to nonvolatile memory and takes a minimum of
t
WR
to complete. The transfer can occur between one of
the four potentiometers and one of its associated
registers; or it may occur globally, wherein the transfer
occurs between all of the potentiometers and one of
their associated registers.
Four instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9258; either between the host and one of
the data registers or directly between the host and the
Wiper Counter Register. These instructions are: Read
Wiper Counter Register (read the current wiper position
of the selected pot), Write Wiper Counter Register
(change current wiper position of the selected pot),
Read Data Register (read the contents of the selected
nonvolatile register) and Write Data Register (write a
new value to the selected data register). The sequence
of operations is shown in Figure 4.
The four high order bits define the instruction. The next
two bits (R1 and R0) select one of the four registers that
is to be acted upon when a register oriented instruction
is issued. The last bits (P1, P0) select which one of the
four potentiometers is to be affected by the instruction.
Four of the nine instructions end with the transmission
of the instruction byte. The basic sequence is illustrated
in Figure 3. These two-byte instructions exchange data
between the Wiper Counter Register and one of the
data registers. A transfer from a Data Register to a
Wiper Counter Register is essentially a write to a static
Figure 3. Two-Byte Instruction Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1
A3
A2
A1
A0
A
C
K
I3
I2
I1
I0
R1 R0 P1 P0
A
C
K
S
T
O
P
The Increment/Decrement command is different from
the other commands. Once the command is issued and
the X9258 has responded with an acknowledge, the
master can clock the selected wiper up and/or down in
one segment steps; thereby, providing a fine tuning
capability to the host. For each SCL clock pulse (t
HIGH
)
while SDA is HIGH, the selected wiper will move one
resistor segment towards the V
H
terminal. Similarly, for
each SCL clock pulse while SDA is LOW, the selected
wiper will move one resistor segment towards the V
L
/R
L
terminal. A detailed illustration of the sequence and
timing for this operation are shown in Figures 5 and 6
respectively.
REV 1.1.7 2/4/03
www.xicor.com
Characteristics subject to change without notice.
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