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82801IBMICH9M: DescriptionIntel I/O Controller Hub 9; File Size6MB，884 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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Intel I/O Controller Hub 9

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Intel

I/O Controller Hub 9 (ICH9)

Family

Datasheet

– For the Intel

82801IB ICH9, 82801IR ICH9R, 82801IH ICH9DH,

82801IO ICH9DO, 82801IBM ICH9M and 82801IEM ICH9M-E,

and ICH9M-SFF ICH9-I/O Controller Hubs

August 2008

Document Number: 316972-004

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL

PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR

OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS

OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING

TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,

MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for

use in medical, life saving, or life sustaining applications.

Legal Lines and Disclaimers

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel

I/O Controller Hub 9 (ICH9) Family chipset component may contain design defects or errors known as errata which may cause the product to

deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I

C bus/protocol and was developed by Intel.

Implementations of the I

C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips

Corporation.

Intel

Active Management Technology requires the computer system to have an Intel

AMT-enabled chipset, network hardware and software, as well as

connection with a power source and a corporate network connection. Setup requires configuration by the purchaser and may require scripting with the

management console or further integration into existing security frameworks to enable certain functionality. It may also require modifications of

implementation of new business processes. With regard to notebooks, Intel AMT may not be available or certain capabilities may be limited over a host

OS-based VPN or when connecting wirelessly, on battery power, sleeping, hibernating or powered off. For more information, see www.intel.com/

technology/platform-technology/intel-amt/

Intel

Virtualization Technology requires a computer system with a processor, chipset, BIOS, virtual machine monitor (VMM) and for some uses, certain

platform software enabled for it. Functionality, performance or other benefit will vary depending on hardware and software configurations and may

require a BIOS update. Software applications may not be compatible with all operating systems. Please check with your application vendor.

Intel, Intel SpeedStep, Intel Viiv, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States

and other countries.

*Other names and brands may be claimed as the property of others.

Intel

I/O Controller Hub 9 (ICH9) Family Datasheet

Contents

Introduction

............................................................................................................ 43

1.1

About This Document......................................................................................... 43

1.2

Overview ......................................................................................................... 47

1.2.1 Capability Overview ................................................................................ 49

1.3

Intel

ICH9 Family High-Level Component Differences ........................................... 54

Signal Description

................................................................................................... 55

2.1

Direct Media Interface (DMI) to Host Controller ..................................................... 58

2.2

PCI Express* .................................................................................................... 59

2.3

LAN Connect Interface ....................................................................................... 59

2.4

Gigabit LAN Connect Interface ............................................................................ 60

2.5

Firmware Hub Interface...................................................................................... 61

2.6

PCI Interface .................................................................................................... 62

2.7

Serial ATA Interface........................................................................................... 64

2.8

LPC Interface.................................................................................................... 67

2.9

Interrupt Interface ............................................................................................ 68

2.10 USB Interface ................................................................................................... 69

2.11 Power Management Interface.............................................................................. 71

2.12 Processor Interface............................................................................................ 74

2.13 SMBus Interface................................................................................................ 75

2.14 System Management Interface............................................................................ 76

2.15 Real Time Clock Interface ................................................................................... 78

2.16 Other Clocks..................................................................................................... 78

2.17 Miscellaneous Signals ........................................................................................ 78

2.18 Intel

High Definition Audio Link ......................................................................... 80

2.19 Serial Peripheral Interface (SPI) .......................................................................... 81

2.20 Controller Link .................................................................................................. 82

2.21 Intel® Quiet System Technology (Desktop Only) ................................................... 83

2.22 General Purpose I/O Signals ............................................................................... 83

2.23 Power and Ground Signals .................................................................................. 86

2.24 Pin Straps ........................................................................................................ 88

2.24.1 Functional Straps ................................................................................... 88

2.24.2 External RTC Circuitry ............................................................................. 90

Intel

ICH9 Pin States.............................................................................................

3.1

Integrated Pull-Ups and Pull-Downs ..................................................................... 91

3.2

Output and I/O Signals Planes and States............................................................. 92

3.3

Power Planes for Input Signals .......................................................................... 101

Intel

ICH9 and System Clock Domains.................................................................

107

Functional Description

........................................................................................... 109

5.1

DMI-to-PCI Bridge (D30:F0) ............................................................................. 109

5.1.1 PCI Bus Interface ................................................................................. 109

5.1.2 PCI Bridge As an Initiator ...................................................................... 109

5.1.2.1 Memory Reads and Writes........................................................ 110

5.1.2.2 I/O Reads and Writes .............................................................. 110

5.1.2.3 Configuration Reads and Writes ................................................ 110

5.1.2.4 Locked Cycles ........................................................................ 110

5.1.2.5 Target / Master Aborts............................................................. 110

5.1.2.6 Secondary Master Latency Timer............................................... 110

5.1.2.7 Dual Address Cycle (DAC) ........................................................ 110

5.1.2.8 Memory and I/O Decode to PCI................................................. 111

Intel

I/O Controller Hub 9 (ICH9) Family Datasheet

5.2

5.3

5.4

5.5

5.1.3 Parity Error Detection and Generation...................................................... 111

5.1.4 PCIRST# ............................................................................................. 112

5.1.5 Peer Cycles .......................................................................................... 112

5.1.6 PCI-to-PCI Bridge Model ........................................................................ 112

5.1.7 IDSEL to Device Number Mapping ........................................................... 113

5.1.8 Standard PCI Bus Configuration Mechanism.............................................. 113

PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5) ................................................ 113

5.2.1 Interrupt Generation ............................................................................. 113

5.2.2 Power Management............................................................................... 114

5.2.2.1 S3/S4/S5 Support ................................................................... 114

5.2.2.2 Resuming from Suspended State ............................................... 114

5.2.2.3 Device Initiated PM_PME Message ............................................. 114

5.2.2.4 SMI/SCI Generation................................................................. 115

5.2.3 SERR# Generation ................................................................................ 115

5.2.4 Hot-Plug .............................................................................................. 116

5.2.4.1 Presence Detection .................................................................. 116

5.2.4.2 Message Generation ................................................................ 116

5.2.4.3 Attention Button Detection ....................................................... 117

5.2.4.4 SMI/SCI Generation................................................................. 117

Gigabit Ethernet Controller (B0:D25:F0) ............................................................. 117

5.3.1 Gigabit Ethernet PCI Bus Interface .......................................................... 118

5.3.1.1 Transaction Layer.................................................................... 118

5.3.1.2 Data Alignment ....................................................................... 118

5.3.1.3 Configuration Request Retry Status ........................................... 119

5.3.2 Error Events and Error Reporting ............................................................ 119

5.3.2.1 Data Parity Error ..................................................................... 119

5.3.2.2 Completion with Unsuccessful Completion Status ......................... 119

5.3.3 Ethernet Interface ................................................................................ 119

5.3.3.1 MAC/LAN Connect Interface ...................................................... 119

5.3.4 PCI Power Management ......................................................................... 120

5.3.4.1 Wake-Up................................................................................ 120

5.3.5 Configurable LEDs................................................................................. 121

5.3.6 Function Level Reset Support (FLR) ......................................................... 122

5.3.6.1 FLR Steps............................................................................... 122

LPC Bridge (w/ System and Management Functions) (D31:F0) ............................... 123

5.4.1 LPC Interface ....................................................................................... 123

5.4.1.1 LPC Cycle Types ...................................................................... 124

5.4.1.2 Start Field Definition ................................................................ 124

5.4.1.3 Cycle Type / Direction (CYCTYPE + DIR)..................................... 125

5.4.1.4 Size....................................................................................... 125

5.4.1.5 SYNC..................................................................................... 126

5.4.1.6 SYNC Time-Out ....................................................................... 126

5.4.1.7 SYNC Error Indication .............................................................. 126

5.4.1.8 LFRAME# Usage...................................................................... 127

5.4.1.9 I/O Cycles .............................................................................. 127

5.4.1.10 Bus Master Cycles ................................................................... 127

5.4.1.11 LPC Power Management ........................................................... 127

5.4.1.12 Configuration and Intel

ICH9 Implications................................. 128

DMA Operation (D31:F0) .................................................................................. 128

5.5.1 Channel Priority.................................................................................... 129

5.5.1.1 Fixed Priority .......................................................................... 129

5.5.1.2 Rotating Priority ...................................................................... 129

5.5.2 Address Compatibility Mode ................................................................... 129

5.5.3 Summary of DMA Transfer Sizes ............................................................. 130

5.5.3.1 Address Shifting When Programmed for 16-Bit I/O Count by Words 130

5.5.4 Autoinitialize ........................................................................................ 130

5.5.5 Software Commands ............................................................................. 131

Intel

I/O Controller Hub 9 (ICH9) Family Datasheet

5.6

5.7

5.8

5.9

5.10

LPC DMA ........................................................................................................ 131

5.6.1 Asserting DMA Requests........................................................................ 131

5.6.2 Abandoning DMA Requests .................................................................... 132

5.6.3 General Flow of DMA Transfers............................................................... 132

5.6.4 Terminal Count .................................................................................... 133

5.6.5 Verify Mode ......................................................................................... 133

5.6.6 DMA Request Deassertion...................................................................... 133

5.6.7 SYNC Field / LDRQ# Rules..................................................................... 134

8254 Timers (D31:F0) ..................................................................................... 135

5.7.1 Timer Programming .............................................................................. 135

5.7.2 Reading from the Interval Timer............................................................. 136

5.7.2.1 Simple Read........................................................................... 136

5.7.2.2 Counter Latch Command.......................................................... 137

5.7.2.3 Read Back Command .............................................................. 137

8259 Interrupt Controllers (PIC) (D31:F0) .......................................................... 138

5.8.1 Interrupt Handling................................................................................ 139

5.8.1.1 Generating Interrupts.............................................................. 139

5.8.1.2 Acknowledging Interrupts ........................................................ 139

5.8.1.3 Hardware/Software Interrupt Sequence ..................................... 140

5.8.2 Initialization Command Words (ICWx) ..................................................... 140

5.8.2.1 ICW1 .................................................................................... 140

5.8.2.2 ICW2 .................................................................................... 141

5.8.2.3 ICW3 .................................................................................... 141

5.8.2.4 ICW4 .................................................................................... 141

5.8.3 Operation Command Words (OCW) ......................................................... 141

5.8.4 Modes of Operation .............................................................................. 141

5.8.4.1 Fully Nested Mode................................................................... 141

5.8.4.2 Special Fully-Nested Mode........................................................ 142

5.8.4.3 Automatic Rotation Mode (Equal Priority Devices)........................ 142

5.8.4.4 Specific Rotation Mode (Specific Priority).................................... 142

5.8.4.5 Poll Mode............................................................................... 142

5.8.4.6 Cascade Mode ........................................................................ 143

5.8.4.7 Edge and Level Triggered Mode ................................................ 143

5.8.4.8 End of Interrupt (EOI) Operations ............................................. 143

5.8.4.9 Normal End of Interrupt........................................................... 143

5.8.4.10 Automatic End of Interrupt Mode .............................................. 143

5.8.5 Masking Interrupts ............................................................................... 144

5.8.5.1 Masking on an Individual Interrupt Request................................ 144

5.8.5.2 Special Mask Mode.................................................................. 144

5.8.6 Steering PCI Interrupts ......................................................................... 144

Advanced Programmable Interrupt Controller (APIC) (D31:F0) .............................. 145

5.9.1 Interrupt Handling................................................................................ 145

5.9.2 Interrupt Mapping ................................................................................ 145

5.9.3 PCI / PCI Express* Message-Based Interrupts .......................................... 146

5.9.4 Front Side Bus Interrupt Delivery ........................................................... 146

5.9.4.1 Edge-Triggered Operation ........................................................ 147

5.9.4.2 Level-Triggered Operation........................................................ 147

5.9.4.3 Registers Associated with Front Side Bus Interrupt Delivery.......... 147

5.9.4.4 Interrupt Message Format ........................................................ 147

5.9.5 IOxAPIC Address Remapping ................................................................. 148

5.9.6 External Interrupt Controller Support ...................................................... 148

Serial Interrupt (D31:F0) ................................................................................. 149

5.10.1 Start Frame......................................................................................... 149

5.10.2 Data Frames........................................................................................ 150

5.10.3 Stop Frame ......................................................................................... 150

5.10.4 Specific Interrupts Not Supported via SERIRQ .......................................... 150

Intel

I/O Controller Hub 9 (ICH9) Family Datasheet

82801IBMICH9M Related Products

	82801IBMICH9M	316972-004	82801IBICH9	82801IEMICH9M-E	82801IHICH9DH	82801IOICH9DO	82801IRICH9R	ICH9M-SFF
Description	Intel I/O Controller Hub 9	Intel I/O Controller Hub 9	Intel I/O Controller Hub 9	Intel I/O Controller Hub 9	Intel I/O Controller Hub 9	Intel I/O Controller Hub 9	Intel I/O Controller Hub 9	Intel I/O Controller Hub 9

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