Intel
®
G35 Express Chipset
Datasheet
— For the 82G35 Graphics and Memory Controller Hub (GMCH)
August 2007
Document Number:
317607-001
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®
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Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from
future changes to them.
The Intel 82G35 GMCH may contain design defects or errors known as errata, which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Hyper-Threading Technology requires a computer system with an Intel® Pentium® 4 processor supporting Hyper-Threading
Technology and an HT Technology enabled chipset, BIOS and operating system. Performance will vary depending on the specific
hardware and software you use. See http://www.intel.com/info/hyperthreading/ for more information including details on which
processors support HT Technology.
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2
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Copyright
©
2007, Intel Corporation
2
Datasheet
Contents
1
Introduction ...................................................................................................18
1.1
1.2
1.3
Terminology ........................................................................................20
Reference Documents ...........................................................................22
GMCH Overview ...................................................................................23
1.3.1
Host Interface.........................................................................23
1.3.2
System Memory Interface.........................................................24
1.3.3
Direct Media Interface (DMI).....................................................25
1.3.4
PCI Express* Interface.............................................................25
1.3.5
Graphics Features ...................................................................26
1.3.6
SDVO and Analog Display Features ............................................26
1.3.7
GMCH Clocking .......................................................................27
1.3.8
Power Management .................................................................28
1.3.9
Thermal Sensor ......................................................................28
Host Interface Signals ...........................................................................31
DDR2 DRAM Channel A Interface ............................................................34
DDR2 DRAM Channel B Interface ............................................................35
DDR2 DRAM Reference and Compensation ...............................................36
PCI Express* Interface Signals ...............................................................36
Analog Display Signals ..........................................................................36
Clocks, Reset, and Miscellaneous ............................................................37
Direct Media Interface (DMI)..................................................................38
Controller Link (CL) ..............................................................................39
Intel
®
Serial DVO (SDVO) Interface ........................................................39
2.10.1 SDVO/PCI Express* Signal Mapping ...........................................41
Power, Ground .....................................................................................42
2
Signal Description ...........................................................................................30
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
3
System Address Map .......................................................................................44
3.1
Legacy Address Range ..........................................................................46
3.1.1
DOS Range (0h – 9_FFFFh).......................................................48
3.1.2
Legacy Video Area (A_0000h–B_FFFFh) ......................................48
3.1.3
Expansion Area (C_0000h–D_FFFFh)..........................................48
3.1.4
Extended System BIOS Area (E_0000h-E_FFFFh).........................49
3.1.5
System BIOS Area (F_0000h – F_FFFFh) ....................................49
3.1.6
PAM Memory Area Details.........................................................50
3.1.7
Legacy Interrupt Routing ..........................................................50
Main Memory Address Range (1MB – TOLUD) ...........................................50
3.2.1
ISA Hole (15MB-16MB) ............................................................51
3.2.2
TSEG.....................................................................................51
3.2.3
Pre-allocated Memory ..............................................................52
PCI Memory Address Range (TOLUD – 4GB) .............................................52
3.3.1
APIC Configuration Space (FEC0_0000h–FECF_FFFFh) ..................54
3.3.2
HSEG (FEDA_0000h–FEDB_FFFFh).............................................54
3.3.3
FSB Interrupt Memory Space (FEE0_0000–FEEF_FFFFh) ............... 54
3.2
3.3
Datasheet
3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
4
3.3.4
High BIOS Area.......................................................................54
Main Memory Address Space (4 GB to TOUUD) .........................................55
3.4.1
Memory Re-claim Background ...................................................56
3.4.2
Memory Reclaiming .................................................................56
PCI Express* Configuration Address Space...............................................56
PCI Express* Graphics Attach (PEG)........................................................57
Graphics Memory Address Ranges...........................................................58
System Management Mode (SMM) ..........................................................58
3.8.1
SMM Space Definition ..............................................................59
3.8.2
SMM Space Restrictions............................................................59
3.8.3
SMM Space Combinations .........................................................60
3.8.4
SMM Control Combinations .......................................................60
3.8.5
SMM Space Decode and Transaction Handling..............................61
3.8.6
Processor WB Transaction to an Enabled SMM Address Space ........61
3.8.7
SMM Access Through GTT TLB ...................................................61
Memory Shadowing ..............................................................................62
I/O Address Space................................................................................62
3.10.1 PCI Express* I/O Address Mapping ............................................63
MCH Decode Rules and Cross-Bridge Address Mapping...............................63
3.11.1 Legacy VGA and I/O Range Decode Rules ...................................64
Register Terminology ............................................................................67
Configuration Process and Registers ........................................................68
4.2.1
Platform Configuration Structure ...............................................68
Configuration Mechanisms .....................................................................69
4.3.1
Standard PCI Configuration Mechanism ......................................69
4.3.2
PCI Express* Enhanced Configuration Mechanism ........................70
Routing Configuration Accesses ..............................................................71
4.4.1
Internal Device Configuration Accesses.......................................72
4.4.2
Bridge Related Configuration Accesses........................................73
I/O Mapped Registers ...........................................................................74
4.5.1
CONFIG_ADDRESS—Configuration Address Register ..................... 74
4.5.2
CONFIG_DATA—Configuration Data Register ............................... 76
DRAM Controller (D0:F0).......................................................................78
5.1.1
VID—Vendor Identification........................................................80
5.1.2
DID—Device Identification ........................................................80
5.1.3
PCICMD—PCI Command ...........................................................81
5.1.4
PCISTS—PCI Status .................................................................82
5.1.5
RID—Revision Identification ......................................................83
5.1.6
CC—Class Code.......................................................................84
5.1.7
MLT—Master Latency Timer ......................................................84
5.1.8
HDR—Header Type ..................................................................85
5.1.9
SVID—Subsystem Vendor Identification......................................85
5.1.10 SID—Subsystem Identification ..................................................85
5.1.11 CAPPTR—Capabilities Pointer ....................................................86
5.1.12 PXPEPBAR—PCI Express* Egress Port Base Address .....................86
5.1.13 MCHBAR—GMCH Memory Mapped Register Range Base ................87
5.1.14 GGC—GMCH Graphics Control ...................................................88
5.1.15 DEVEN—Device Enable.............................................................89
5.1.16 PCIEXBAR—PCI Express* Register Range Base Address ................90
Datasheet
GMCH Register Description ...............................................................................66
4.1
4.2
4.3
4.4
4.5
5
DRAM Controller Registers (D0:F0)....................................................................78
5.1
4
5.2
5.1.17 DMIBAR—Root Complex Register Range Base Address ..................92
5.1.18 PAM0—Programmable Attribute Map 0........................................93
5.1.19 PAM1—Programmable Attribute Map 1........................................95
5.1.20 PAM2—Programmable Attribute Map 2........................................96
5.1.21 PAM3—Programmable Attribute Map 3........................................97
5.1.22 PAM4—Programmable Attribute Map 4........................................98
5.1.23 PAM5—Programmable Attribute Map 5........................................99
5.1.24 PAM6—Programmable Attribute Map 6...................................... 100
5.1.25 LAC—Legacy Access Control.................................................... 101
5.1.26 REMAPBASE—Remap Base Address Register.............................. 102
5.1.27 REMAPLIMIT—Remap Limit Address Register ............................. 102
5.1.28 SMRAM—System Management RAM Control .............................. 103
5.1.29 ESMRAMC—Extended System Management RAM Control ............. 104
5.1.30 TOM—Top of Memory............................................................. 105
5.1.31 TOUUD—Top of Upper Usable Dram ......................................... 106
5.1.32 GBSM—Graphics Base of Stolen Memory................................... 107
5.1.33 TSEGMB—TSEG Memory Base ................................................. 107
5.1.34 TOLUD—Top of Low Usable DRAM ............................................ 108
5.1.35 ERRSTS—Error Status ............................................................ 109
5.1.36 ERRCMD—Error Command ...................................................... 110
5.1.37 SMICMD—SMI Command........................................................ 111
5.1.38 SKPD—Scratchpad Data ......................................................... 111
5.1.39 CAPID0—Capability Identifier .................................................. 112
MCHBAR ........................................................................................... 113
5.2.1
CHDECMISC—Channel Decode Miscellaneous............................. 116
5.2.2
C0DRB0—Channel 0 DRAM Rank Boundary Address 0 ................. 117
5.2.3
C0DRB1—Channel 0 DRAM Rank Boundary Address 1 ................. 118
5.2.4
C0DRB2—Channel 0 DRAM Rank Boundary Address 2 ................. 119
5.2.5
C0DRB3—Channel 0 DRAM Rank Boundary Address 3 ................. 119
5.2.6
C0DRA01—Channel 0 DRAM Rank 0,1 Attribute ......................... 120
5.2.7
C0DRA23—Channel 0 DRAM Rank 2,3 Attribute ......................... 121
5.2.8
C0CYCTRKPCHG—Channel 0 CYCTRK PCHG............................... 121
5.2.9
C0CYCTRKACT—Channel 0 CYCTRK ACT ................................... 122
5.2.10 C0CYCTRKWR—Channel 0 CYCTRK WR ..................................... 123
5.2.11 C0CYCTRKRD—Channel 0 CYCTRK READ................................... 124
5.2.12 C0CYCTRKREFR—Channel 0 CYCTRK REFR ................................ 124
5.2.13 C0CKECTRL—Channel 0 CKE Control ........................................ 125
5.2.14 C0REFRCTRL—Channel 0 DRAM Refresh Control......................... 126
5.2.15 C0ODTCTRL—Channel 0 ODT Control ....................................... 128
5.2.16 C1DRB0—Channel 1 DRAM Rank Boundary Address 0 ................. 129
5.2.17 C1DRB1—Channel 1 DRAM Rank Boundary Address 1 ................. 129
5.2.18 C1DRB2—Channel 1 DRAM Rank Boundary Address 2 ................. 130
5.2.19 C1DRB3—Channel 1 DRAM Rank Boundary Address 3 ................. 130
5.2.20 C1DRA01—Channel 1 DRAM Rank 0,1 Attributes ........................ 131
5.2.21 C1DRA23—Channel 1 DRAM Rank 2,3 Attributes ........................ 131
5.2.22 C1CYCTRKPCHG—Channel 1 CYCTRK PCHG............................... 132
5.2.23 C1CYCTRKACT—Channel 1 CYCTRK ACT ................................... 133
5.2.24 C1CYCTRKWR—Channel 1 CYCTRK WR ..................................... 134
5.2.25 C1CYCTRKRD—Channel 1 CYCTRK READ................................... 135
5.2.26 C1CKECTRL—Channel 1 CKE Control ........................................ 136
5.2.27 C1REFRCTRL—Channel 1 DRAM Refresh Control......................... 137
5.2.28 C1ODTCTRL—Channel 1 ODT Control ....................................... 139
5.2.29 EPC0DRB0—ME Channel 0 DRAM Rank Boundary Address 0........ 140
5.2.30 EPC0DRB1—ME Channel 0 DRAM Rank Boundary Address 1 ........ 140
5.2.31 EPC0DRB2— ME Channel 0 DRAM Rank Boundary Address 2........ 141
Datasheet
5
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