Intel
®
X38 Express Chipset
Datasheet
— For the Intel
®
82X38 Memory Controller Hub (MCH)
October 2007
Document Number: 317610-001
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®
82X38Memory Controller Hub (MCH) may contain design defects or errors known as errata, which may cause the product to deviate from
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®
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2
Datasheet
Contents
1
Introduction
............................................................................................................ 15
1.1
Terminology ..................................................................................................... 16
1.2
MCH Overview .................................................................................................. 19
1.2.1 Host Interface........................................................................................ 19
1.2.2 System Memory Interface ....................................................................... 19
1.2.3 Direct Media Interface (DMI).................................................................... 20
1.2.4 PCI Express* Interface............................................................................ 21
1.2.5 MCH Clocking ........................................................................................ 22
1.2.6 Power Management ................................................................................ 22
1.2.7 Thermal Sensor ..................................................................................... 22
Signal Description
................................................................................................... 23
2.1
Host Interface Signals........................................................................................ 24
2.2
System Memory (DDR2/DDR3) Interface Signals ................................................... 27
2.2.1 System Memory Channel A Interface Signals.............................................. 27
2.2.2 System Memory Channel B Interface Signals.............................................. 28
2.2.3 System Memory Miscellaneous Signals ...................................................... 29
2.3
PCI Express* Interface Signals ............................................................................ 30
2.4
Controller Link Interface Signals .......................................................................... 30
2.5
Clocks, Reset, and Miscellaneous ......................................................................... 31
2.6
Direct Media Interface........................................................................................ 32
2.7
Power and Grounds ........................................................................................... 32
System Address Map
............................................................................................... 33
3.1
Legacy Address Range ....................................................................................... 36
3.1.1 DOS Range (0h – 9_FFFFh) ..................................................................... 36
3.1.2 Expansion Area (C_0000h-D_FFFFh) ......................................................... 37
3.1.3 Extended System BIOS Area (E_0000h–E_FFFFh) ....................................... 37
3.1.4 System BIOS Area (F_0000h–F_FFFFh) ..................................................... 38
3.1.5 PAM Memory Area Details........................................................................ 38
3.2
Main Memory Address Range (1MB – TOLUD)........................................................ 38
3.2.1 ISA Hole (15 MB –16 MB) ........................................................................ 39
3.2.2 TSEG .................................................................................................... 40
3.2.3 Pre-allocated Memory ............................................................................. 40
3.3
PCI Memory Address Range (TOLUD
–
4 GB) ........................................................ 41
3.3.1 APIC Configuration Space (FEC0_0000h–FECF_FFFFh)................................. 43
3.3.2 HSEG (FEDA_0000h–FEDB_FFFFh) ........................................................... 43
3.3.3 FSB Interrupt Memory Space (FEE0_0000–FEEF_FFFF)................................ 43
3.3.4 High BIOS Area...................................................................................... 43
3.4
Main Memory Address Space (4 GB to TOUUD)...................................................... 44
3.4.1 Memory Re-claim Background .................................................................. 45
3.4.2 Memory Reclaiming ................................................................................ 45
3.5
PCI Express* Configuration Address Space ........................................................... 45
3.6
PCI Express* Address Space ............................................................................... 46
3.7
System Management Mode (SMM) ....................................................................... 47
3.7.1 SMM Space Definition ............................................................................. 47
3.7.2 SMM Space Restrictions .......................................................................... 48
3.7.3 SMM Space Combinations........................................................................ 48
3.7.4 SMM Control Combinations ...................................................................... 49
3.7.5 SMM Space Decode and Transaction Handling ............................................ 49
3.7.6 Processor WB Transaction to an Enabled SMM Address Space ....................... 49
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Datasheet
3
3.8
3.9
4
3.7.7 SMM Access Through TLB.........................................................................49
Memory Shadowing............................................................................................50
I/O Address Space .............................................................................................50
3.9.1 PCI Express* I/O Address Mapping............................................................51
MCH Register Description.........................................................................................53
4.1
Register Terminology .........................................................................................54
4.2
Configuration Process and Registers .....................................................................55
4.2.1 Platform Configuration Structure...............................................................55
4.3
Configuration Mechanisms ..................................................................................56
4.3.1 Standard PCI Configuration Mechanism......................................................56
4.3.2 PCI Express Enhanced Configuration Mechanism .........................................57
4.4
Routing Configuration Accesses ...........................................................................58
4.4.1 Internal Device Configuration Accesses ......................................................59
4.4.2 Bridge Related Configuration Accesses.......................................................60
4.4.2.1 PCI Express Configuration Accesses .............................................60
4.4.2.2 DMI Configuration Accesses ........................................................60
4.5
I/O Mapped Registers.........................................................................................61
4.5.1 CONFIG_ADDRESS—Configuration Address Register ....................................61
4.5.2 CONFIG_DATA—Configuration Data Register ..............................................62
DRAM Controller Registers (D0:F0)
..........................................................................63
5.1
Configuration Register Details..............................................................................65
5.1.1 VID—Vendor Identification .......................................................................65
5.1.2 DID—Device Identification .......................................................................65
5.1.3 PCICMD—PCI Command ..........................................................................66
5.1.4 PCISTS—PCI Status ................................................................................67
5.1.5 RID—Revision Identification .....................................................................68
5.1.6 CC—Class Code ......................................................................................68
5.1.7 MLT—Master Latency Timer......................................................................68
5.1.8 HDR—Header Type .................................................................................69
5.1.9 SVID—Subsystem Vendor Identification .....................................................69
5.1.10 SID—Subsystem Identification..................................................................69
5.1.11 CAPPTR—Capabilities Pointer ....................................................................70
5.1.12 PXPEPBAR—PCI Express* Egress Port Base Address ....................................70
5.1.13 MCHBAR—MCH Memory Mapped Register Range Base .................................71
5.1.14 DEVEN—Device Enable ............................................................................72
5.1.15 PCIEXBAR—PCI Express* Register Range Base Address ...............................73
5.1.16 DMIBAR—Root Complex Register Range Base Address .................................75
5.1.17 PAM0—Programmable Attribute Map 0 .......................................................76
5.1.18 PAM1—Programmable Attribute Map 1 .......................................................77
5.1.19 PAM2—Programmable Attribute Map 2 .......................................................78
5.1.20 PAM3—Programmable Attribute Map 3 .......................................................79
5.1.21 PAM4—Programmable Attribute Map 4 .......................................................80
5.1.22 PAM5—Programmable Attribute Map 5 .......................................................81
5.1.23 PAM6—Programmable Attribute Map 6 .......................................................82
5.1.24 LAC—Legacy Access Control .....................................................................83
5.1.25 REMAPBASE—Remap Base Address Register...............................................83
5.1.26 REMAPLIMIT—Remap Limit Address Register ..............................................84
5.1.27 SMRAM—System Management RAM Control................................................85
5.1.28 ESMRAMC—Extended System Management RAM Control ..............................86
5.1.29 TOM—Top of Memory ..............................................................................87
5.1.30 TOUUD—Top of Upper Usable Dram ..........................................................87
5.1.31 BSM—Base of Stolen Memory ...................................................................88
5.1.32 TSEGMB—TSEG Memory Base ..................................................................88
5.1.33 TOLUD—Top of Low Usable DRAM .............................................................89
5.1.34 ERRSTS—Error Status .............................................................................90
5.1.35 ERRCMD—Error Command .......................................................................92
5.1.36 SMICMD—SMI Command .........................................................................93
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Datasheet
5.2
5.3
5.1.37 SKPD—Scratchpad Data .......................................................................... 93
5.1.38 CAPID0—Capability Identifier ................................................................... 94
MCHBAR .......................................................................................................... 97
5.2.1 CHDECMISC—Channel Decode Misc .......................................................... 99
5.2.2 C0DRB0—Channel 0 DRAM Rank Boundary Address 0 ............................... 100
5.2.3 C0DRB1—Channel 0 DRAM Rank Boundary Address 1 ............................... 101
5.2.4 C0DRB2—Channel 0 DRAM Rank Boundary Address 2 ............................... 102
5.2.5 C0DRB3—Channel 0 DRAM Rank Boundary Address 3 ............................... 102
5.2.6 C0DRA01—Channel 0 DRAM Rank 0,1 Attribute ........................................ 103
5.2.7 C0DRA23—Channel 0 DRAM Rank 2,3 Attribute ........................................ 104
5.2.8 C0CYCTRKPCHG—Channel 0 CYCTRK PCHG ............................................. 104
5.2.9 C0CYCTRKACT—Channel 0 CYCTRK ACT .................................................. 105
5.2.10 C0CYCTRKWR—Channel 0 CYCTRK WR.................................................... 106
5.2.11 C0CYCTRKRD—Channel 0 CYCTRK READ ................................................. 107
5.2.12 C0CYCTRKREFR—Channel 0 CYCTRK REFR............................................... 107
5.2.13 C0CKECTRL—Channel 0 CKE Control ....................................................... 108
5.2.14 C0REFRCTRL—Channel 0 DRAM Refresh Control ....................................... 109
5.2.15 C0ECCERRLOG—Channel 0 ECC Error Log................................................ 111
5.2.16 C0ODTCTRL—Channel 0 ODT Control ...................................................... 112
5.2.17 C1DRB0—Channel 1 DRAM Rank Boundary Address 0 ............................... 112
5.2.18 C1DRB1—Channel 1 DRAM Rank Boundary Address 1 ............................... 113
5.2.19 C1DRB2—Channel 1 DRAM Rank Boundary Address 2 ............................... 113
5.2.20 C1DRB3—Channel 1 DRAM Rank Boundary Address 3 ............................... 114
5.2.21 C1DRA01—Channel 1 DRAM Rank 0,1 Attributes....................................... 114
5.2.22 C1DRA23—Channel 1 DRAM Rank 2,3 Attributes....................................... 114
5.2.23 C1CYCTRKPCHG—Channel 1 CYCTRK PCHG ............................................. 115
5.2.24 C1CYCTRKACT—Channel 1 CYCTRK ACT .................................................. 115
5.2.25 C1CYCTRKWR—Channel 1 CYCTRK WR.................................................... 116
5.2.26 C1CYCTRKRD—Channel 1 CYCTRK READ ................................................. 117
5.2.27 C1CKECTRL—Channel 1 CKE Control ....................................................... 118
5.2.28 C1REFRCTRL—Channel 1 DRAM Refresh Control ....................................... 119
5.2.29 C1ECCERRLOG—Channel 1 ECC Error Log................................................ 120
5.2.30 C1ODTCTRL—Channel 1 ODT Control ...................................................... 121
5.2.31 EPC0DRB0—EP Channel 0 DRAM Rank Boundary Address 0........................ 122
5.2.32 EPC0DRB1—EP Channel 0 DRAM Rank Boundary Address 1........................ 122
5.2.33 EPC0DRB2—EP Channel 0 DRAM Rank Boundary Address 2........................ 122
5.2.34 EPC0DRB3—EP Channel 0 DRAM Rank Boundary Address 3........................ 123
5.2.35 EPC0DRA01—EP Channel 0 DRAM Rank 0,1 Attribute ................................ 123
5.2.36 EPC0DRA23—EP Channel 0 DRAM Rank 2,3 Attribute ................................ 124
5.2.37 EPDCYCTRKWRTPRE—EPD CYCTRK WRT PRE ........................................... 124
5.2.38 EPDCYCTRKWRTACT—EPD CYCTRK WRT ACT ........................................... 125
5.2.39 EPDCYCTRKWRTWR—EPD CYCTRK WRT WR............................................. 125
5.2.40 EPDCYCTRKWRTREF—EPD CYCTRK WRT REF ........................................... 126
5.2.41 EPDCYCTRKWRTRD—EPD CYCTRK WRT READ .......................................... 126
5.2.42 EPDCKECONFIGREG—EPD CKE Related Configuration ................................ 127
5.2.43 EPDREFCONFIG—EP DRAM Refresh Configuration ..................................... 128
5.2.44 TSC1—Thermal Sensor Control 1 ............................................................ 130
5.2.45 TSC2—Thermal Sensor Control 2 ............................................................ 131
5.2.46 TSS—Thermal Sensor Status ................................................................. 133
5.2.47 TSTTP—Thermal Sensor Temperature Trip Point ....................................... 134
5.2.48 TCO—Thermal Calibration Offset ............................................................ 135
5.2.49 THERM1—Thermal Hardware Protection................................................... 136
5.2.50 TIS—Thermal Interrupt Status ............................................................... 136
5.2.51 TSMICMD—Thermal SMI Command......................................................... 138
5.2.52 PMSTS—Power Management Status ........................................................ 139
EPBAR ........................................................................................................... 140
5.3.1 EPESD—EP Element Self Description ....................................................... 140
5.3.2 EPLE1D—EP Link Entry 1 Description....................................................... 141
5.3.3 EPLE1A—EP Link Entry 1 Address ........................................................... 141
5.3.4 EPLE2D—EP Link Entry 2 Description....................................................... 142
Datasheet
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