Intel® Celeron® M Processor
on 90 nm Process
Datasheet
January 2007
Document Number: 303110-008
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future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
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specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Δ
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Copyright© 2004–2007, Intel Corporation. All rights reserved.
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Datasheet
Contents
1
Introduction
.............................................................................................................. 7
1.1
Terminology ....................................................................................................... 8
1.2
References ......................................................................................................... 8
Low Power Features
................................................................................................ 11
2.1
Clock Control and Low Power States .................................................................... 11
2.1.1 Normal State ......................................................................................... 11
2.1.2 AutoHALT Power-Down State ................................................................... 11
2.1.3 Stop-Grant State.................................................................................... 11
2.1.4 HALT/Grant Snoop State ......................................................................... 12
2.1.5 Sleep State ........................................................................................... 12
2.1.6 Deep Sleep State ................................................................................... 13
2.2
FSB Low Power Enhancements ............................................................................ 13
2.3
Processor Power Status Indicator (PSI#) Signal..................................................... 14
Electrical Specifications
........................................................................................... 15
3.1
Power and Ground Pins ...................................................................................... 15
3.1.1 FSB Clock (BCLK[1:0]) and Processor Clocking ........................................... 15
3.2
Voltage Identification and Power Sequencing ........................................................ 15
3.3
Catastrophic Thermal Protection .......................................................................... 17
3.4
Signal Terminations and Unused Pins ................................................................... 17
3.5
FSB Frequency Select Signals (BSEL[1:0])............................................................ 17
3.6
FSB Signal Groups............................................................................................. 17
3.7
CMOS Signals ................................................................................................... 19
3.8
Maximum Ratings.............................................................................................. 19
3.9
Processor DC Specifications ................................................................................ 19
Package Mechanical Specifications and Pin Information
.......................................... 29
4.1
Processor Pinout and Pin List .............................................................................. 37
4.2
Alphabetical Signals Reference ............................................................................ 55
Thermal Specifications and Design Considerations
.................................................. 63
5.1
Thermal Specifications ....................................................................................... 65
5.1.1 Thermal Diode ....................................................................................... 65
5.1.2 Thermal Diode Offset .............................................................................. 66
5.1.3 Intel® Thermal Monitor........................................................................... 67
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3
4
5
Datasheet
3
Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
Clock Control States .................................................................................................11
Illustration of Deep Sleep State VCC Static and Ripple Tolerances
for the Celeron M Processor (Deep Sleep State): VID=1.260 V .......................................22
Illustration of Active State VCC Static and Ripple Tolerances
for the Celeron M Processor ULV: VID=0.940 V ............................................................24
Illustration of Deep Sleep State VCC Static and Ripple Tolerances
for the Celeron M Processor ULV: VID=0.940 V ............................................................25
Active VCC and ICC Loadline for the Celeron M Processor:
Standard Voltage and Ultra Low Voltage ......................................................................25
Deep Sleep VCC and ICC Loadline for Celeron M Processors:
Standard Voltage and Ultra Low Voltage ......................................................................26
Micro-FCPGA Package Top and Bottom Isometric Views .................................................29
Micro-FCPGA Package - Top and Side Views .................................................................30
Micro-FCPGA Package - Bottom View...........................................................................31
Micro-FCBGA Package Top and Bottom Isometric Views .................................................33
Micro-FCBGA Package Top and Side Views ...................................................................34
Micro-FCBGA Package Bottom View.............................................................................36
The Coordinates of the Processor Pins As Viewed from the Top of the Package ..................38
Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Voltage Identification Definition ..................................................................................16
FSB Pin Groups ........................................................................................................18
Processor DC Absolute Maximum Ratings.....................................................................19
Voltage and Current Specifications..............................................................................20
Voltage Tolerances for the Celeron M Processor (Deep Sleep State).................................22
Voltage Tolerances for the Celeron M Processor ULV (Active State)..................................23
Voltage Tolerances for the Celeron M Processor ULV (Deep Sleep State) ..........................24
FSB Differential BCLK Specifications ............................................................................26
AGTL+ Signal Group DC Specifications ........................................................................27
CMOS Signal Group DC Specifications..........................................................................27
Open Drain Signal Group DC Specifications ..................................................................28
Micro-FCPGA Package Dimensions ..............................................................................32
Micro-FCPGA Package Dimensions ..............................................................................35
Pin Listing by Pin Name .............................................................................................39
Pin Listing by Pin Number ..........................................................................................46
Signal Description.....................................................................................................55
Power Specifications for the Celeron M Processor ..........................................................64
Thermal Diode Interface ............................................................................................66
Thermal Diode Specification .......................................................................................66
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Datasheet
Revision History
Revision
-001
Initial release
Updates include:
• Document Title from “Intel® Celeron® M Processor Ultra Low
Voltage on 90 nm Process” to “Intel® Celeron® M Processor on
90 nm Process”
• Added Micro-FCPGA package information throughout Chapter 4
• Celeron® M Processor 360 and 350 DC and Thermal and Power
Specifications (Updated
Table 4
and
Table 17)
Updates include:
• Added resources to the Reference Table 1
• BSEL[1:] literature updated
• Celeron M processor 370 and 373 DC and Thermal and Power
Specifications (Updated
Table 4
and
Table 17)
• Execute Disable bit and Lead Free feature referenced
•
•
•
-006
•
-007
-008
•
•
Celeron M processor 383 DC and Thermal and Power Specifications
(Updated Table
Table 4
and
Table 17)
Added Celeron M processor 380 specifications
Updated Celeron M processor 370, 360J, 350J and Celeron M
processor ULV 383, 373 specifications for optimized VID (T
Table 4
and
Table 17)
Updated Celeron M processor ULV 383, 373 TDP specification
(Table
17)
Added Celeron M processor 390 specifications
Updated Celeron M 390 Thermal Specifications
Description
Date
July 2004
-002
August 2004
-003
January 2005
-004
-005
April 2005
July 2005
July 2005
January 2006
January 2007
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Datasheet
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