Intel
®
Celeron
®
D Processor
300
Δ
Sequence
Datasheet
– On 65 nm Process in the 775-Land Package
March 2007
Document Number: 311826-005
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INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS.
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Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel
®
Celeron
®
D processor 300 sequence on 65 nm process may contain design defects or errors known as errata which may cause the product to
deviate from published specifications.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Δ
Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different
processor families. Over time processor numbers will increment based on changes in clock speed, cache, FSB, or other features, and increments are not
intended to represent proportional or quantitative increases in any particular feature. Current roadmap processor number progression is not necessarily
representative of future roadmaps. See
http://www.intel.com/products/processor_number
for details.
Intel
®
64 requires a computer system with a processor, chipset, BIOS, operating system, device drivers, and applications enabled for Intel 64. Processor
will not operate (including 32-bit operation) without an Intel 64-enabled BIOS. Performance will vary depending on your hardware and software
configurations. See http://www.intel.com/technology/intel64/index.htm for more information including details on which processors support Intel 64, or
consult with your system vendor for more information.
Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check
with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.
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*Other names and brands may be claimed as the property of others.
Copyright © 2006–2007 Intel Corporation.
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Datasheet
Contents
1
Introduction................................................................................................................. 9
1.1
Terminology ....................................................................................................... 9
1.1.1 Processor Packaging Terminology ............................................................. 10
1.2
References ....................................................................................................... 11
Electrical Specifications ............................................................................................... 13
2.1
Power and Ground Lands.................................................................................... 13
2.2
Decoupling Guidelines ........................................................................................ 13
2.2.1 VCC Decoupling ..................................................................................... 13
2.2.2 VTT Decoupling ...................................................................................... 14
2.2.3 FSB Decoupling...................................................................................... 14
2.3
Voltage Identification ......................................................................................... 14
2.4
Reserved, Unused, and TESTHI Signals ................................................................ 16
2.5
Voltage and Current Specification ........................................................................ 17
2.5.1 Absolute Maximum and Minimum Ratings .................................................. 17
2.5.2 DC Voltage and Current Specification ........................................................ 18
2.5.3 VCC Overshoot ...................................................................................... 21
2.5.4 Die Voltage Validation ............................................................................. 22
2.6
Signaling Specifications...................................................................................... 22
2.6.1 FSB Signal Groups.................................................................................. 23
2.6.2 GTL+ Asynchronous Signals..................................................................... 25
2.6.3 Processor DC Specifications ..................................................................... 25
2.6.3.1 GTL+ Front Side Bus Specifications ............................................. 28
2.7
Clock Specifications ........................................................................................... 29
2.7.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking ............................ 29
2.7.2 FSB Frequency Select Signals (BSEL[2:0])................................................. 30
2.7.3 Phase Lock Loop (PLL) and Filter .............................................................. 30
2.7.4 BCLK[1:0] Specifications ......................................................................... 32
Package Mechanical Specifications ................................................................................ 33
3.1
Package Mechanical Drawing............................................................................... 33
3.2
Processor Component Keep-Out Zones ................................................................. 37
3.3
Package Loading Specifications ........................................................................... 37
3.4
Package Handling Guidelines............................................................................... 37
3.5
Package Insertion Specifications.......................................................................... 38
3.6
Processor Mass Specification ............................................................................... 38
3.7
Processor Materials............................................................................................ 38
3.8
Processor Markings............................................................................................ 38
3.9
Processor Land Coordinates ................................................................................ 39
Land Listing and Signal Descriptions ............................................................................. 41
4.1
Processor Land Assignments ............................................................................... 41
4.2
Alphabetical Signals Reference ............................................................................ 64
Thermal Specifications and Design Considerations........................................................... 75
5.1
Processor Thermal Specifications ......................................................................... 75
5.1.1 Thermal Specifications ............................................................................ 75
5.1.2 Thermal Metrology ................................................................................. 79
5.2
Processor Thermal Features ................................................................................ 79
5.2.1 Thermal Monitor..................................................................................... 79
5.2.2 On-Demand Mode .................................................................................. 80
5.2.3 PROCHOT# Signal .................................................................................. 81
5.2.4 THERMTRIP# Signal ............................................................................... 81
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3
4
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Datasheet
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5.2.5
5.2.6
6
T
CONTROL
and Fan Speed Reduction ...........................................................81
Thermal Diode........................................................................................81
Features ....................................................................................................................85
6.1
Power-On Configuration Options ..........................................................................85
6.2
Clock Control and Low Power States .....................................................................85
6.2.1 Normal State .........................................................................................86
6.2.2 HALT and Enhanced HALT Powerdown States..............................................86
6.2.2.1 HALT Powerdown State ..............................................................87
6.2.2.2 Enhanced HALT Powerdown State................................................87
6.2.3 Stop Grant State ....................................................................................87
6.2.4 Enhanced HALT Snoop or HALT Snoop State,
Stop Grant Snoop State...........................................................................88
6.2.4.1 HALT Snoop State, Stop Grant Snoop State ..................................88
6.2.4.2 Enhanced HALT Snoop State .......................................................88
Boxed Processor Specifications .....................................................................................89
7.1
Mechanical Specifications ....................................................................................89
7.1.1 Boxed Processor Cooling Solution Dimensions.............................................89
7.1.2 Boxed Processor Fan Heatsink Weight .......................................................91
7.1.3 Boxed Processor Retention Mechanism and Heatsink
Attach Clip Assembly...............................................................................91
7.2
Electrical Requirements ......................................................................................91
7.2.1 Fan Heatsink Power Supply ......................................................................91
7.3
Thermal Specifications........................................................................................93
7.3.1 Boxed Processor Cooling Requirements......................................................93
Debug Tools Specifications ...........................................................................................95
8.1
Logic Analyzer Interface (LAI) .............................................................................95
8.1.1 Mechanical Considerations .......................................................................95
8.1.2 Electrical Considerations ..........................................................................95
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Datasheet
Figures
1
2
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4
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6
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8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
V
CC
Static and Transient Tolerance for 775_VR_CONFIG_05A and 775_VR_CONFIG_06
Processors .............................................................................................................. 21
V
CC
Overshoot Example Waveform ............................................................................. 22
Phase Lock Loop (PLL) Filter Requirements .................................................................. 31
Processor Package Assembly Sketch ........................................................................... 33
Processor Package Drawing (Sheet 1 of 3)................................................................... 34
Processor Package Drawing (Sheet 2 of 3)................................................................... 35
Processor Package Drawing (Sheet 3 of 3)................................................................... 36
Processor Top-Side Marking Example .......................................................................... 38
Processor Land Coordinates and Quadrants (Top View) ................................................. 39
land-out Diagram (Top View – Left Side) ..................................................................... 42
land-out Diagram (Top View – Right Side) ................................................................... 43
Thermal Profile for 775_VR_CONFIG_05A Processors .................................................... 77
Thermal Profile for 775_VR_CONFIG_06 Processors ...................................................... 78
Case Temperature (TC) Measurement Location ............................................................ 79
Processor Low Power State Machine ........................................................................... 86
Mechanical Representation of the Boxed Processor ....................................................... 89
Space Requirements for the Boxed Processor (Side View: applies to all four side views) .... 90
Space Requirements for the Boxed Processor (Top View)............................................... 90
Space Requirements for the Boxed Processor (Overall View) ......................................... 91
Boxed Processor Fan Heatsink Power Cable Connector Description .................................. 92
Baseboard Power Header Placement Relative to Processor Socket ................................... 93
Boxed Processor Fan Heatsink Airspace Keep-out Requirements
(Side 1 View) .......................................................................................................... 94
Boxed Processor Fan Heatsink Airspace Keep-out Requirements
(Side 2 View) .......................................................................................................... 94
Datasheet
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