DATASHEET
X9110
Dual Supply/Low Power/1024-Tap/SPI Bus, Single Digitally-Controlled (XDCP™)
Potentiometer
The
X9110
integrates a Single Digitally Controlled
Potentiometer (XDCP) on a monolithic CMOS integrated circuit.
The digital controlled potentiometer is implemented using
1023 resistive elements in a series array. Between each
element are tap points connected to the wiper terminal
through switches. The position of the wiper on the array is
controlled by the user through the SPI bus interface. The
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and four nonvolatile data registers that can be
directly written to, and read by, the user. The contents of the
WCR controls the position of the wiper on the resistor array
though the switches. Power-up recalls the contents of the
default data register (DR0) to the WCR.
The XDCP can be used as a three-terminal potentiometer or as
a two terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
FN8158
Rev 5.00
October 28, 2016
Features
• 1024 resistor taps – 10-bit resolution
• SPI serial interface for write, read, and transfer operations of
the potentiometer
• Wiper resistance, 40Ωtypical at 5V
• Four nonvolatile data registers
• Nonvolatile storage of multiple wiper positions
• Power-on recall, loads saved wiper position on power-up
• Standby current <5µA maximum
• System V
CC
: 2.7V to 5.5V operation
• Analog V+/V-: -5V to +5V
• 100kΩend-to-end resistance
• 100 year data retention
• Endurance: 100,000 data changes per bit per register
• 14 Ld TSSOP
• Dual supply version of the X9111
• Low power CMOS
• Pb-free (RoHS compliant)
Related Literature
• For a full list of related documents, visit our website
-
X9110
product page
V
CC
R
H
V+
ADDRESS
DATA
STATUS
SPI
BUS
INTERFACE
BUS
INTERFACE
AND
CONTROL
WRITE
READ
TRANSFER
POWER-ON RECALL
WIPER COUNTER
REGISTER (WCR)
DATA REGISTERS
(DR0-DR3)
WIPER
100kΩ
1024-TAPS
POT
CONTROL
V
SS
NC
NC
R
W
R
L
V-
FIGURE 1. FUNCTIONAL DIAGRAM
FN8158 Rev 5.00
October 28, 2016
Page 1 of 18
X9110
Applications
Circuit Level Applications
• Vary the gain of a voltage amplifier
• Provide programmable DC reference voltages for comparators
and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and Q-factor in filter
circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the DC biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback circuits
System Level Applications
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in communication
systems
• Set and regulate the DC biasing point in an RF power amplifier
in wireless systems
• Control the gain in audio and home entertainment systems
• Provide the variable DC bias for tuners in RF wireless systems
• Set the operating points in temperature control systems
• Control the operating point for sensors in industrial systems
• Trim offset and gain errors in artificial intelligent systems
Ordering Information
PART NUMBER
(Notes
2, 3)
X9110TV14Z (Note
1)
X9110TV14IZ
X9110TV14Z-2.7
PART
MARKING
X9110 TVZ
X9110 TVZI
X9110 TVZF
2.7 to 5.5
V
CC
LIMITS
(V)
5 ±10
POTENTIOMETER
RANGE (kΩ)
100
TEMP RANGE
(°C)
0 to +70
-40 to +85
0 to +70
-40 to +85
PACKAGE
(RoHS COMPLIANT)
14 Ld TSSOP
14 Ld TSSOP
14 Ld TSSOP
14 Ld TSSOP
PKG. DWG. #
M14.173
M14.173
M14.173
M14.173
X9110TV14IZ-2.7 (Note
1)
X9110 TVZG
NOTES:
1. Add “T1” suffix for 2.5k unit tape and reel option.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), see product information page for
X9110.
For more information on MSL, see tech brief
TB363.
FN8158 Rev 5.00
October 28, 2016
Page 2 of 18
X9110
Detailed Functional Diagram
V
CC
V+
HOLD
CS
SCK
SO
SI
A0
INTERFACE
AND
CONTROL
CIRCUITRY
POWER ON
RECALL
DR0
DATA
DR2
CONTROL
DR3
DR1
WIPER
COUNTER
REGISTER
(WCR)
100kΩ
1024-TAPS
R
L
R
W
R
H
WP
V
SS
V-
FIGURE 2. DETAILED FUNCTIONAL DIAGRAM
Pin Configuration
X9110
14 LD TSSOP
TOP VIEW
V+
SO
A0
SCK
WP
SI
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
R
L
R
H
R
W
HOLD
CS
V-
Pin Descriptions
PIN
(TSSOP)
11
12
13
14
SYMBOL
R
W
R
H
R
L
V
CC
(Continued)
FUNCTION
Wiper Terminal of the Potentiometer
High Terminal of the Potentiometer
Low Terminal of the Potentiometer
System Supply Voltage
Bus Interface Pins
SERIAL OUTPUT (SO)
SO is a serial data output pin. During a read cycle, data is shifted
out on this pin. Data is clocked out on the falling edge of the
serial clock.
Pin Descriptions
PIN
(TSSOP)
1
2
3
4
5
6
7
8
9
10
SYMBOL
V+
SO
A0
SCK
WP
SI
V
SS
V-
CS
HOLD
FUNCTION
Analog Supply Voltage
Serial Data Output
Device Address
Serial Clock
Hardware Write Protect
Serial Data Input
System Ground
Analog Supply Voltage
Chip Select
Device Select. Pause the Serial Bus
SERIAL INPUT (SI)
SI is the serial data input pin. All opcodes, byte addresses and
data to be written to the potentiometer pot registers are input on
this pin. Data is latched by the rising edge of the serial clock.
SERIAL CLOCK (SCK)
The SCK input is used to clock data into and out of the X9110.
HOLD (HOLD)
HOLD is used in conjunction with the CS pin to select the device.
Once the part is selected and a serial sequence is underway,
HOLD may be used to pause the serial communication with the
controller without resetting the serial sequence. To pause, HOLD
must be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while SCK is LOW.
FN8158 Rev 5.00
October 28, 2016
Page 3 of 18
X9110
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
REGISTER 0
(DR0)
10
REGISTER 1
(DR1)
10
SERIAL
BUS
INPUT
C
O
U
N
T
E
R
D
E
C
O
D
E
R
RH
PARALLEL
BUS
INPUT
WIPER
COUNTER
REGISTER
(WCR)
REGISTER 2
(DR2)
REGISTER 3
(DR3)
If WCR = 000[HEX] then R
W
= R
L
If WCR = 3FF[HEX] then R
W
= R
H
RL
R
W
FIGURE 3. DETAILED POTENTIOMETER BLOCK DIAGRAM
If the pause feature is not used, HOLD should be held HIGH at all
times.
Bias Supply Pins
SYSTEM SUPPLY VOLTAGE (V
CC
) AND SUPPLY
GROUND (V
SS
)
The V
CC
pin is the system supply voltage. The V
SS
pin is the
system ground.
DEVICE ADDRESS (A0)
The address input is used to set the 8-bit slave address. A match
in the slave address serial data stream A0 must be made with
the address input (A0) in order to initiate communication with
the X9110.
ANALOG SUPPLY VOLTAGES (V+ AND V-)
These supplies are the analog voltage supplies for the
potentiometer. The V+ supply is tied to the wiper switches while
the V- supply is used to bias the switches and the internal P+
substrate of the integrated circuit. Both of these supplies set the
voltage limits of the potentiometer.
CHIP SELECT (CS)
When CS is HIGH, the X9110 is deselected and the SO pin is at
high impedance, and (unless an internal write cycle is underway)
the device will be in the standby state. CS LOW enables the
X9110, placing it in the active power mode. It should be noted
that after a power-up, a HIGH to LOW transition on CS is required
prior to the start of any operation.
Principles of Operation
Device Description
SERIAL INTERFACE
The X9110 supports the SPI interface hardware conventions. The
device is accessed via the SI input with data clocked-in on the
rising SCK. CS must be LOW and the HOLD and WP pins must be
HIGH during the entire operation.
The SO and SI pins can be connected together, since they have
three state outputs. This can help to reduce system pin count.
HARDWARE WRITE PROTECT INPUT (WP)
The WP pin when LOW prevents nonvolatile writes to the Data
Registers.
Potentiometer Pins
R
H
, R
L
The R
H
and R
L
pins are equivalent to the terminal connections on
a mechanical potentiometer.
R
W
The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer.
ARRAY DESCRIPTION
The X9110 is comprised of a resistor array (Figure
3).
The array
contains the equivalent of 1023 discrete resistive segments that
are connected in series. The physical ends of each array are
equivalent to the fixed terminals of a mechanical potentiometer
(R
H
and R
L
inputs).
FN8158 Rev 5.00
October 28, 2016
Page 4 of 18
X9110
At both ends of each array and between each resistor segment is
a CMOS switch connected to the wiper (R
W
) output. Within the
individual array only one switch may be turned on at a time.
These switches are controlled by a Wiper Counter Register
(WCR). The 10-bits of the WCR (WCR[9:0]) are decoded to select,
and enable, one of 1024 switches.
DATA REGISTERS (DR)
The potentiometer has four 10-bit nonvolatile Data Registers.
These can be read or written directly by the host. Data can also
be transferred between any of the four Data Registers and the
Wiper Counter Register. All operations changing data in one of
the Data Registers is a nonvolatile operation and will take a
maximum of 10ms.
If the application does not require storage of multiple settings for
the potentiometer, the Data Registers can be used as regular
memory locations for system parameters or user preference
data.
DR[9:0] is used to store one of the 1024 wiper position (0~1023)
(see
Table 2).
WIPER COUNTER REGISTER (WCR)
The X9110 contains a Wiper Counter Register (see
Table 1)
for
the XDCP potentiometer. The WCR is equivalent to a serial-in,
parallel-out register/counter with its outputs decoded to select
one of 1024 switches along its resistor array. The content of the
WCR can be altered in one of three ways: (1) it may be written
directly by the host via the write Wiper Counter Register
instruction (serial load); (2) it may be written indirectly by
transferring the content of one of four associated Data Registers
via the XFR Data Register; (3) it is loaded with the content of its
data register zero (DR0) upon power-up.
The Wiper Counter Register is a volatile register; that is, its content is
lost when the X9110 is powered-down. Although the register is
automatically loaded with the value in DR0 upon power-up, this
may be different from the value present at power-down.
Power-up guidelines are recommended to ensure proper
loadings of the DR0 value into the WCR.
STATUS REGISTER (SR)
This 1-bit status register is used to store the system status (see
Table 3).
WIP: Write In Progress status bit, read only.
• When WIP = 1, indicates that high-voltage write cycle is in
progress.
• When WIP = 0, indicates that no high-voltage write cycle is in
progress.
TABLE 1. WIPER CONTROL REGISTER, WCR (10-BIT), WCR9–WCR0: Used to store the current wiper position (Volatile, V)
WCR9
V
(MSB)
TABLE 2. DATA REGISTER, DR (10-BIT), BIT 9–BIT 0: Used to store wiper positions or data (Nonvolatile, NV)
BIT 9
NV
(MSB)
TABLE 3. STATUS REGISTER, SR (1-BIT)
WIP
(LSB)
TABLE 4. IDENTIFICATION BYTE FORMAT
DEVICE TYPE
IDENTIFIER
INTERNAL SLAVE
ADDRESS
WCR8
V
WCR7
V
WCR6
V
WCR5
V
WCR4
V
WCR3
V
WCR2
V
WCR1
V
WCR0
V
(LSB)
BIT 8
NV
BIT 7
NV
BIT 6
NV
BIT 5
NV
BIT 4
NV
BIT 3
NV
BIT 2
NV
BIT 1
NV
BIT 0
NV
(LSB)
READ OR
WRITE BIT
ID3
0
(MSB)
ID2
1
ID1
0
ID0
1
0
0
A0
R/W
(LSB)
FN8158 Rev 5.00
October 28, 2016
Page 5 of 18
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