Data Sheet
A m p l i fy t h e H u m a n E x p e r i e n c e
CDK1307
Ultra Low Power, 10/20/40/65/80/100MSPS,
12/13-bit Analog-to-Digital Converters (ADCs)
CDK1307
Ultra Low Power, 10/20/40/65/80/100MSPS, 12/13-bit ADCs
FEATURES
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General Description
The CDK1307 is a high performance ultra low power Analog-to-Digital
Converter (ADC). The ADC employs internal reference circuitry, a CMOS
control interface and CMOS output data, and is based on a proprietary struc-
ture. Digital error correction is employed to ensure no missing codes in the
complete full scale range.
Two idle modes with fast startup times exist. The entire chip can either be
put in Standby Mode or Power Down mode. The two modes are optimized to
allow the user to select the mode resulting in the smallest possible energy
consumption during idle mode and startup.
The CDK1307 has a highly linear THA optimized for frequencies up to Nyquist.
The differential clock interface is optimized for low jitter clock sources and
supports LVDS, LVPECL, sine wave, and CMOS clock inputs.
13-bit resolution
10/20/40/65/80/100MSPS max
sampling rate
Ultra-Low Power Dissipation:
17/19/33/50/60/75mW
72.4dB SNR at 80MSPS and 8MHz F
IN
Internal reference circuitry
1.8V core supply voltage
1.7 – 3.6V I/O supply voltage
Parallel CMOS output
40-pin QFN package
Pin compatible with CDK1308
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APPLICATIONS
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Medical Imaging
Portable Test Equipment
Digital Oscilloscopes
IF Communication
Functional Block Diagram
Ordering Information
Part Number
CDK1307ILP40
CDK1307AILP40
CDK1307BILP40
CDK1307CILP40
CDK1307DILP40
CDK1307EILP40
Speed
10MSPS
20MSPS
40MSPS
65MSPS
80MSPS
100MSPS
Package
QFN-40
QFN-40
QFN-40
QFN-40
QFN-40
QFN-40
Pb-Free
Yes
Yes
Yes
Yes
Yes
Yes
RoHS Compliant
Yes
Yes
Yes
Yes
Yes
Yes
Operating Temperature Range
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Packaging Method
Tray
Tray
Tray
Tray
Tray
Tray
Rev 1A
Moisture sensitivity level for all parts is MSL-2A.
©2009 CADEKA Microcircuits LLC
www.cadeka.com
Data Sheet
Pin Configuration
CM_EXTBC_0
CM_EXTBC_1
QFN-40
SLP_N
OVDD
OVDD
D_12
D_10
D_11
D_9
D_8
CDK1307
Ultra Low Power, 10/20/40/65/80/100MSPS, 12/13-bit ADCs
40
39
38
37
36
35
34
33
32
DVDD
CM_EXT
AVDD
AVDD
IP
IN
AVDD
DVDDCLK
CLKP
CLKN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
31
30
29
28
D_7
D_6
D_5
CLK_EXT
OVDD
OVDD
ORNG
D_4
D_3
D_2
CDK1307
QFN-40
27
26
25
24
23
22
21
DFRMT
OE_N
OVDD
OVDD
DVDD
DVDD
D_0
Pin Assignments
Pin No.
0
1, 11, 16
2
3, 4, 7
5, 6
8
9
10
12
13
14
15
17, 18, 25,
26, 36, 37
19
20
21
22
Pin Name
VSS
DVDD
CM_EXT
AVDD
IP, IN
DVDDCLK
CLKP
CLKN
CLK_EXT_EN
DFRMT
PD_N
OE_N
OVDD
D_0
D_1
D_2
D_3
Description
Ground connection for all power domains. Exposed pad
Digital and I/O-ring pre driver supply voltage, 1.8V
Common Mode voltage output
Analog supply voltage, 1.8V
Analog input (non-inverting, inverting)
Clock circuitry supply voltage, 1.8V
Clock input, non-inverting (format: LVDS, LVPECL, CMOS/TTL, Sine Wave)
Clock input, inverting. For CMOS input on CLKP, Connect CLKN to ground
CLK_EXT signal enabled when low (zero). Tristate when high.
Data format selection. 0: Offset Binary, 1: Two's Complement
Full chip Power Down mode when Low. All digital outputs reset to zero. After chip power up
always apply Power Down mode before using Active Mode to reset chip.
Output Enable. Tristate when high
I/O ring post-driver supply voltage. Voltage range 1.7 to 3.6V
Output Data (LSB, 13-bit output or 1V
pp
full scale range)
Output Data (LSB, 12-bit output 2V
pp
full scale range)
Output Data
Output Data
CLK_EXT_EN
PD_N
D_1
Rev 1A
©2009 CADEKA Microcircuits LLC
www.cadeka.com
2
Data Sheet
Pin Assignments
(Continued)
Pin No.
23
24
27
28
29
30
31
32
33
34
35
38, 39
Pin Name
D_4
ORNG
CLK_EXT
D_5
D_6
D_7
D_8
D_9
D_10
D_11
D_12
CM_EXTBC_1,
CM_EXTBC_0
SLP_N
Description
Output Data
Out of Range flag. High when input signal is out of range
Output clock signal for data synchronization. CMOS levels
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data (MSB for 1V
pp
full scale range, see Reference Voltages section)
Output Data (MSB for 2V
pp
full scale range)
Bias control bits for the buffer driving pin CM_EXT
00: OFF
10: 500μA
40
01: 50μA
11: 1mA
CDK1307
Ultra Low Power, 10/20/40/65/80/100MSPS, 12/13-bit ADCs
Sleep Mode when low
Rev 1A
©2009 CADEKA Microcircuits LLC
www.cadeka.com
3
Data Sheet
Absolute Maximum Ratings
The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device
should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper device
function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the
operating conditions noted on the tables and plots.
Parameter
AVDD
DVDD
AVSS, DVSSCK, DVSS, OVSS
OVDD, OVSS
CLKP, CLKN
Analog inputs and outpts (IPx, INx)
Digital inputs
Digital outputs
Min
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
Max
+2.3
+2.3
+0.3
+3.9
+3.9
+2.3
+3.9
+3.9
Unit
V
V
V
V
V
V
V
V
CDK1307
Ultra Low Power, 10/20/40/65/80/100MSPS, 12/13-bit ADCs
Reliability Information
Parameter
Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10s)
Min
-60
J-STD-020
Typ
Max
TBD
+150
Unit
°C
°C
ESD Protection
Product
Human Body Model (HBM)
QFN-40
2kV
Recommended Operating Conditions
Parameter
Operating Temperature Range
Min
-40
Typ
Max
+85
Unit
°C
Rev 1A
©2009 CADEKA Microcircuits LLC
www.cadeka.com
4
Data Sheet
Electrical Characteristics
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20/40/65/80MSPS clock, 50% clock duty cycle,
-1dBFS 8MHz input signal, 13-bit output, unless otherwise noted)
Symbol
DC Accuracy
No Missing Codes
Offset Error
Gain Error
DNL
INL
V
CMO
Differential Non-Linearity
Integral Non-Linearity
Common Mode Voltage Output
Input Common Mode
Full Scale Range, Normal
V
FSR
Full Scale Range, Option
Input Capacitance
Bandwidth
Analog input common mode voltage
Differential input voltage range,
Differential input voltage range, 1V
(see section Reference Voltages)
Differential input capacitance
Input bandwidth, full power
Supply voltage to all 1.8V domain pins.
See Pin Configuration and Description
Output driver supply voltage (OVDD).
Must be higher than or equal to Core Supply
Voltage (V
OVDD
≥ V
OCVDD
)
500
1.7
1.7
1.8
2.5
2.0
3.6
V
CM
-0.1
2.0
1.0
2
Midscale offset
Full scale range deviation from typical
12-bit level
12-bit level
-6
±0.2
±0.6
V
AVDD
/2
V
CM
+0.2
Guaranteed
1
6
mV
%FS
LSB
LSB
V
V
V
pp
V
pp
pF
MHz
V
V
Parameter
Conditions
Min
Typ
Max
Units
CDK1307
Ultra Low Power, 10/20/40/65/80/100MSPS, 12/13-bit ADCs
Analog Input
V
CMI
Power Supply
AVDD,
DVDD
OVDD
Core Supply Voltage
I/O Supply Voltage
Rev 1A
©2009 CADEKA Microcircuits LLC
www.cadeka.com
5
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