MCM63Z819TQ15 datasheet, PDF - EEWORLD Datasheet

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MCM63Z819TQ15: DescriptionIC,SYNC SRAM,256KX18,CMOS,QFP,100PIN,PLASTIC; Categorystorage storage; File Size374KB，20 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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MCM63Z819TQ15 Overview

IC,SYNC SRAM,256KX18,CMOS,QFP,100PIN,PLASTIC

MCM63Z819TQ15 Parametric

Parameter Name	Attribute value
Maker	NXP
Parts packaging code	QFP
package instruction	LQFP,
Contacts	100
Reach Compliance Code	unknown
ECCN code	3A991
Maximum access time	15 ns
Other features	FLOW-THROUGH ARCHITECTURE
JESD-30 code	R-PQFP-G100
length	20 mm
memory density	4718592 bit
Memory IC Type	ZBT SRAM
memory width	18
Number of functions	1
Number of terminals	100
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	256KX18
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
width	14 mm

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MOTOROLA

Freescale Semiconductor, Inc.

SEMICONDUCTOR TECHNICAL DATA

Order this document

by MCM63Z737/D

128K x 36 and 256K x 18 Bit

Flow–Through ZBT™ RAM

Synchronous Fast Static RAM

MCM63Z737

MCM63Z819

Freescale Semiconductor, Inc...

The ZBT RAM is a 4M–bit synchronous fast static RAM designed to provide

Zero Bus Turnaround™. The ZBT RAM allows 100% use of bus cycles during

back–to–back read/write and write/read cycles. The MCM63Z737 (organized as

128K words by 36 bits) and the MCM63Z819 (organized as 256K words by 18

bits) are fabricated in Motorola’s high performance silicon gate CMOS

technology. This device integrates input registers, a 2–bit address counter, and

high speed SRAM onto a single monolithic circuit for reduced parts count in

communication applications. Synchronous design allows precise cycle control

with the use of an external clock (CK). CMOS circuitry reduces the overall power

consumption of the integrated functions for greater reliability.

Addresses (SA), data inputs (DQ), and all control signals except output enable

(G) and linear burst order (LBO) are clock (CK) controlled through positive–

edge–triggered noninverting registers.

Write cycles are internally self–timed and are initiated by

rising edge of the

the

clock (CK) input. This feature eliminates complex off–chip write pulse generation

and provides increased timing flexibility for incoming signals.

For read cycles, a flow–through SRAM allows output data to simply flow freely

from the memory array.

TQ PACKAGE

TQFP

CASE 983A–01

•

3.3 V LVTTL and LVCMOS Compatible

10 ns Access / 12 ns Cycle (83 MHz)

•

MCM63Z737/MCM63Z819–10 =

MCM63Z737/MCM63Z819–11 = 11 ns Access / 15 ns Cycle (66 MHz)

MCM63Z737/MCM63Z819–15 = 15 ns Access / 20 ns Cycle (50 MHz)

•

Selectable Burst Sequencing Order (Linear/Interleaved)

•

Internally Self–Timed Write Cycle

•

Single–Cycle Deselect

•

Byte Write Control

•

ADV Controlled Burst

•

100–Pin TQFP Package

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by

Micron Technology, Inc. and Motorola, Inc.

REV 5

1/14/00

Motorola, Inc. 2000

MOTOROLA FAST SRAM

For More Information On This Product,

Go to: www.freescale.com

MCM63Z737

MCM63Z819

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