M95512-WDW3P/K datasheet, PDF - EEWORLD Datasheet

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M95512-WDW3P/K: Description64K X 8 SPI BUS SERIAL EEPROM, PDSO8; Categorystorage; File Size335KB，48 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/

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M95512-WDW3P/K Overview

64K X 8 SPI BUS SERIAL EEPROM, PDSO8

M95512-WDW3P/K Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	8
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	5.5 V
Minimum supply/operating voltage	1.8 V
Rated supply voltage	2.5 V
maximum clock frequency	5 MHz
Processing package description	0.150 INCH, ROHS COMPLIANT, PLASTIC, SON-8
state	ACTIVE
Craftsmanship	CMOS
packaging shape	Rectangle
Package Size	SMALL OUTLINE
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	1.27 mm
terminal coating	NOT SPECIFIED
Terminal location	pair
Packaging Materials	Plastic/Epoxy
Temperature level	INDUSTRIAL
memory width	8
organize	64K × 8
storage density	524288 deg
operating mode	Synchronize
Number of digits	65536 words
Number of digits	64K
Memory IC type	bus serial electrically erasable read-only memory
serial parallel	serial
Maximum TWC of write cycle	5 ms

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M95512-DR

M95512-R M95512-W

512 Kbit serial SPI bus EEPROM

with high-speed clock

Features

■

Compatible with the Serial Peripheral Interface

(SPI) bus

Memory array

– 512 Kb (64 Kbytes) of EEPROM

– Page size: 128 bytes

Additional Write lockable Page (Identification

page)

Write

– Byte Write within 5 ms

– Page Write within 5 ms

Write Protect: quarter, half or whole memory

array

High-speed clock frequency (20 MHz)

Single supply voltage: 1.8 V to 5.5 V

More than 1 Million Write cycles

More than 40-year data retention

Enhanced ESD Protection

Packages

– ECOPACK2® (RoHS compliant and

Halogen-free)

WLCSP (CS)

TSSOP8 (DW)

169 mils width

SO8 (MN)

150 mils width

■

UFDFPN8 (MB)

2 × 3 mm (MLP)

September 2010

Doc ID 11124 Rev 13

1/48

www.st.com

Contents

M95512-W, M95512-R

Contents

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1

SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1

Supply voltage (V

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1.1

4.1.2

4.1.3

4.1.4

Operating supply voltage V

CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.2

4.3

4.4

4.5

Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 13

Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.1

6.2

6.3

Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.3.1

WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2/48

Doc ID 11124 Rev 13

List of tables

M95512-W, M95512-R

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Table 26.

Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

M95512-W and M95512-R instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

M95512-DR instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Operating conditions (M95512-W device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Operating conditions (M95512-W device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Operating conditions (M95512-R and M95512-DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

DC characteristics (current M95512-W products). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

DC characteristics (new M95512-W products) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

DC characteristics (current and new M95512-R and M95512-DR products) . . . . . . . . . . . 33

AC characteristics (current M95512-W products) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

AC characteristics (New M95512-W products) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

AC characteristics (current and new M95512-R and M95512-DR products) . . . . . . . . . . . 36

SO8N – 8 lead plastic small outline, 150 mils body width, package

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

TSSOP8 – 8 lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 40

UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead

2 × 3 .mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

WLCSP-R – 8-bump wafer-length chip-scale package mechanical data . . . . . . . . . . . . . . 42

Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Available M95512 products (package, voltage range, temperature grade) . . . . . . . . . . . . 44

Available M95512-DR products (package, voltage range, temperature grade) . . . . . . . . . 44

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4/48

Doc ID 11124 Rev 13

M95512-W, M95512-R

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Figure 10.

Figure 11.

Figure 12.

Figure 13.

Figure 14.

Figure 15.

Figure 16.

Figure 17.

Figure 18.

Figure 19.

Figure 20.

Figure 21.

Figure 22.

Figure 23.

Figure 24.

Figure 25.

Figure 26.

Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

SO8, TSSOP8 and UFDFPN8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

WLCSP connections (top view, marking side, with balls on the underside) . . . . . . . . . . . . 7

Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Read Identification Page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Write Identification Page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Read Lock Status sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Lock ID sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

SO8N – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 39

TSSOP8 – 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 40

UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead

2 × 3 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

WLCSP-R – 8-bump wafer-length chip-scale package outline . . . . . . . . . . . . . . . . . . . . . . 42

Doc ID 11124 Rev 13

5/48

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