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SN74LVC2G04
DUAL INVERTER GATE
www.ti.com
SCES195K – APRIL 1999 – REVISED MARCH 2006
FEATURES
•
•
•
•
•
•
•
•
Available in the Texas Instruments
NanoStar™ and NanoFree™ Packages
Supports 5-V V
CC
Operation
Inputs Accept Voltages to 5.5 V
Max t
pd
of 4.1 ns at 3.3 V
Low Power Consumption, 10-µA Max I
CC
±24-mA
Output Drive at 3.3 V
Typical V
OLP
(Output Ground Bounce) <0.8 V
at V
CC
= 3.3 V, T
A
= 25°C
Typical V
OHV
(Output V
OH
Undershoot) >2 V at
V
CC
= 3.3 V, T
A
= 25°C
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
•
•
•
I
off
Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DRL PACKAGE
(TOP VIEW)
YEA, YEP, YZA,
OR YZP PACKAGE
(BOTTOM VIEW)
1A
GND
2A
1
6
1Y
V
CC
2Y
1A
GND
1
2
3
6
5
4
1Y
V
CC
2Y
1A
GND
2A
1
2
3
6
5
4
1Y
V
CC
2Y
2A
GND
1A
3 4
2 5
1 6
2Y
V
CC
1Y
2
5
2A
3
4
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
ORDERING INFORMATION
T
A
PACKAGE
(1)
NanoStar™ – WCSP (DSBGA)
0.17-mm Small Bump – YEA
NanoFree™ – WCSP (DSBGA)
0.17-mm Small Bump – YZA
(Pb-free)
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YEP
–40°C to 85°C
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP
(Pb-free)
SOT (SOT-23) – DBV
SOT (SC-70) – DCK
SOT (SOT-563) – DRL
(1)
(2)
Reel of 3000
Reel of 250
Reel of 3000
Reel of 250
Reel of 4000
ORDERABLE PART NUMBER
SN74LVC2G04YEAR
SN74LVC2G04YZAR
Reel of 3000
SN74LVC2G04YEPR
SN74LVC2G04YZPR
SN74LVC2G04DBVR
SN74LVC2G04DBVT
SN74LVC2G04DCKR
SN74LVC2G04DCKT
SN74LVC2G04DRLR
_ _ _CC_
TOP-SIDE MARKING
(2)
C04_
CC_
CC_
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA,YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb,
•
= Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2006, Texas Instruments Incorporated
SN74LVC2G04
DUAL INVERTER GATE
SCES195K – APRIL 1999 – REVISED MARCH 2006
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
This dual inverter is designed for 1.65-V to 5.5-V V
CC
operation. The SN74LVC2G04 performs the Boolean
function Y = A.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
FUNCTION TABLE
(EACH INVERTER)
INPUT
A
H
L
OUTPUT
Y
L
H
LOGIC DIAGRAM (POSITIVE LOGIC)
1A
1
6
1Y
2A
3
4
2Y
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
V
CC
V
I
V
O
V
O
I
IK
I
OK
I
O
Supply voltage range
Input voltage range
(2)
Voltage range applied to any output in the high-impedance or power-off
Voltage range applied to any output in the high or low state
(2) (3)
Input clamp current
Output clamp current
Continuous output current
Continuous current through V
CC
or GND
DBV package
DCK package
θ
JA
Package thermal impedance
(4)
DRL package
YEA/YZA package
YEP/YZP package
T
stg
(1)
(2)
(3)
(4)
Storage temperature range
–65
V
I
< 0
V
O
< 0
state
(2)
–0.5
–0.5
–0.5
–0.5
MAX
6.5
6.5
6.5
V
CC
+ 0.5
–50
–50
±50
±100
165
259
142
143
123
150
°C
°C/W
UNIT
V
V
V
V
mA
mA
mA
mA
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The value of V
CC
is provided in the recommended operating conditions table.
The package thermal impedance is calculated in accordance with JESD 51-7.
2
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www.ti.com
SN74LVC2G04
DUAL INVERTER GATE
SCES195K – APRIL 1999 – REVISED MARCH 2006
Recommended Operating Conditions
(1)
MIN
V
CC
Supply voltage
Operating
Data retention only
V
CC
= 1.65 V to 1.95 V
V
IH
High-level input voltage
V
CC
= 2.3 V to 2.7 V
V
CC
= 3 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
CC
= 1.65 V to 1.95 V
V
IL
Low-level input voltage
V
CC
= 2.3 V to 2.7 V
V
CC
= 3 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
I
V
O
Input voltage
Output voltage
V
CC
= 1.65 V
V
CC
= 2.3 V
I
OH
High-level output current
V
CC
= 3 V
V
CC
= 4.5 V
V
CC
= 1.65 V
V
CC
= 2.3 V
I
OL
Low-level output current
V
CC
= 3 V
V
CC
= 4.5 V
V
CC
= 1.8 V
±
0.15 V, 2.5 V
±
0.2 V
∆t/∆v
T
A
(1)
Input transition rise or fall rate
Operating free-air temperature
V
CC
= 3.3 V
±
0.3 V
V
CC
= 5 V
±
0.5 V
–40
0
0
1.65
1.5
0.65
×
V
CC
1.7
2
0.7
×
V
CC
0.35
×
V
CC
0.7
0.8
0.3
×
V
CC
5.5
V
CC
–4
–8
–16
–24
–32
4
8
16
24
32
20
10
5
85
°C
ns/V
mA
mA
V
V
V
V
MAX
5.5
UNIT
V
All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
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3
SN74LVC2G04
DUAL INVERTER GATE
SCES195K – APRIL 1999 – REVISED MARCH 2006
www.ti.com
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
I
OH
= –100
µA
I
OH
= –4 mA
V
OH
I
OH
= –8 mA
I
OH
= –16 mA
I
OH
= –24 mA
I
OH
= –32 mA
I
OL
= 100
µA
I
OL
= 4 mA
V
OL
I
OL
= 8 mA
I
OL
= 16 mA
I
OL
= 24 mA
I
OL
= 32 mA
I
I
I
off
I
CC
∆I
CC
C
i
(1)
A inputs
V
I
= 5.5 V or GND
V
I
or V
O
= 5.5 V
V
I
= 5.5 V or GND,
One input at V
CC
– 0.6 V,
V
I
= V
CC
or GND
All typical values are at V
CC
= 3.3 V, T
A
= 25°C.
I
O
= 0
Other inputs at V
CC
or GND
TEST CONDITIONS
V
CC
1.65 V to 5.5 V
1.65 V
2.3 V
3V
4.5 V
1.65 V to 5.5 V
1.65 V
2.3 V
3V
4.5 V
0 to 5.5 V
0
1.65 V to 5.5 V
3 V to 5.5 V
3.3 V
3.5
MIN TYP
(1)
MAX
V
CC
– 0.1
1.2
1.9
2.4
2.3
3.8
0.1
0.45
0.3
0.4
0.55
0.55
±5
±10
10
500
µA
µA
µA
µA
pF
V
V
UNIT
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see
Figure 1)
PARAMETER
t
pd
FROM
(INPUT)
A
TO
(OUTPUT)
Y
V
CC
= 1.8 V
±
0.15 V
MIN
3.1
MAX
8
V
CC
= 2.5 V
±
0.2 V
MIN
1.5
MAX
4.4
V
CC
= 3.3 V
±
0.3 V
MIN
1.2
MAX
4.1
V
CC
= 5 V
±
0.5 V
MIN
1
MAX
3.2
ns
UNIT
Operating Characteristics
T
A
= 25°C
PARAMETER
C
pd
Power dissipation capacitance
TEST CONDITIONS
f = 10 MHz
V
CC
= 1.8 V
TYP
14
V
CC
= 2.5 V
TYP
14
V
CC
= 3.3 V
TYP
14
V
CC
= 5 V
TYP
16
UNIT
pF
4
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