MoBL
®
Clock
M200/M500
Two-PLL Programmable Clock Generator for
Portable Applications
Features
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Benefits
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Device Operating Voltage Options:
❐
MoBL Clock M200 Family: 1.8V
❐
MoBL Clock M500 Family: 2.5V, 3.0V, or 3.3V
Selectable clock output voltages for both MoBL Clock M200
and M500:
❐
1.5V, 1.8V, 2.5V, 3.0V, or 3.3V
Fully integrated ultra low power phase-locked loops (PLLs)
Input reference clock frequency range: 1–48 MHz
Output clock frequency range: 3–50 MHz
Three I
2
C™ programmable output clocks
Programmable output drive strengths
150 ps typical cycle-to-cycle jitter
Optional Spread Spectrum for EMI reduction
16-pin (3x3x0.6 mm) QFN Package
Industrial temperature range
Suitable for cell phone, portable, and consumer electronics
applications
Multiple high-performance PLLs allow synthesis of unrelated
frequencies
Application compatibility in multiple output voltage levels
Optional Spread Spectrum capable PLLs with Lexmark or
Linear profile for maximum EMI reduction
PLLs can be programmed for system frequency margin tests
Meets critical timing requirements in complex system
designs
Individually enable or disable each output using I
2
C
Ease of output clock selection using programmable crossbar
switches
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Logic Block Diagram
VDD_CLK1
VDD_CLK2
VDD_CLK3
EXCLKIN
REF SEL
CLK1
Crossbar
Switch
PLL1
MUX
and
Control
Logic
Output
Dividers
and
PLL2
(SS)
Drive
Strength
Control
CLK3
CLK2
SCL
SDA
PD#/OE
I2C
Cypress Semiconductor Corporation
Document #: 001-29139 Rev. *A
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised August 10, 2009
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MoBL
®
Clock
M200/M500
Pinouts
MoBL Clock M200
Figure 1. Pin Diagram - 16 LD QFN
EXCLKIN
CLK3
VDD
16
15
14
VSS
1
VSS
13
12
DNU
CLK1
2
MoBL Clock M200
16 LD QFN
11
VDD_CLK3
VDD_CLK1
3
10
VDD_CLK2
PD#/OE
4
9
CLK2
5
VSS
6
SCL
7
SDA
8
VSS
Table 1. Pin Definitions - MoBL Clock M200 Family (VDD = 1.8V Supply)
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VSS
CLK1
VDD_CLK1
PD#/OE
VSS
SCL
SDA
VSS
CLK2
VDD_CLK2
VDD_CLK3
DNU
VSS
CLK3
VDD
EXCLKIN
Name
Power
Output
Power
Input
Power
Input
Input/Output
Power
Output
Power
Power
DNU
Power
Output
Power
Input
IO
GND
Programmable Clock Output. Output voltage depends on
VDD_CLK1 voltage
Power Supply for CLK1: 1.5V/1.8V/2.5V/3.0V/3.3V
Multifunction Programmable pin: Output Enable or Power Down
Modes
GND
I
2
C-Bus Clock Line
I
2
C-Bus Data Line
GND
Programmable Clock Output. Output voltage depends on
VDD_CLK2 voltage
Power Supply for CLK2: 1.5V/1.8V/2.5V/3.0V/3.3V
Power Supply for output CLK3: 1.5V/1.8V/2.5V/3.0V/3.3V
Do Not Use this pin
GND
Programmable Clock Output. Output voltage depends on
VDD_CLK3 voltage
Power Supply: 1.8V
1.8V external Reference Clock
Description
Document #: 001-29139 Rev. *A
Page 2 of 14
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MoBL
®
Clock
M200/M500
MoBL Clock M500
Figure 2. Pin Diagram - 16 LD QFN
EXCLKIN
VDD
CLK3
16
15
14
VSS
1
VSS
13
12
DNU
CLK1
2
MoBL Clock M500
16 LD QFN
11
VDD_CLK3
VDD_CLK1
3
10
VDD_CLK2
PD#/OE
4
9
CLK2
5
VSS
6
SCL
7
SDA
8
VSS
Table 2. Pin Definitions - MoBL Clock M500 Family (VDD = 2.5V, 3.0V or 3.3V Supply)
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VSS
CLK1
VDD_CLK1
PD#/OE
VSS
SCL
SDA
VSS
CLK2
VDD_CLK2
VDD_CLK3
DNU
VSS
CLK3
VDD
EXCLKIN
Name
Power
Output
Power
Input
Power
Input
Input/Output
Power
Output
Power
Power
DNU
Power
Output
Power
Input
IO
GND
Programmable Clock Output. Output voltage depends on
VDD_CLK1 voltage
Power Supply for CLK1: 1.5V/1.8V/2.5V/3.0V/3.3V
Multifunction Programmable pin: Output Enable or Power Down
Modes
GND
I
2
C-Bus Clock Line
I
2
C-Bus Data Line
GND
Programmable Clock Output. Output voltage depends on
VDD_CLK2 voltage
Power Supply for CLK2: 1.5V/1.8V/2.5V/3.0V/3.3V
Power Supply for output CLK3: 1.5V/1.8V/2.5V/3.0V/3.3V
Do Not Use this pin
GND
Programmable Clock Output. Output voltage depends on
VDD_CLK3 voltage
Power Supply: 2.5V/3.0V/3.3V
2.5V/3.0V/3.3V external Reference Clock
Description
Document #: 001-29139 Rev. *A
Page 3 of 14
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MoBL
®
Clock
M200/M500
General Description
2 Configurable PLLs
The MoBL
®
Clock M200/M500 Family of products are two-PLL
Clock Generator ICs designed for cell phone, portable, or
consumer electronics applications. It can be used to generate
two independent output frequencies ranging from 3 to 50MHz
from a single input reference clock.
to ±2.50%, or down spread range from –0.25% to –5.0%, with
Lexmark or Linear modulation profile.
PD#/OE Mode
PD#/OE input (Pin 4) can be programmed to operate as either
power down (PD#) or output enable (OE) mode. Note that power
down shuts off the entire chip, resulting in minimum power
consumption for the device. Setting this signal high brings the
device in the operational mode with default register settings. The
PD# turn-on time is limited by the turn-on time of the PLLs.
Disabled outputs are first driven to a low state before turning off.
When off, they are held low by internal weak resistors (~160k
ohms)
When this pin is programmed as Output Enable (OE), clock
outputs can be enabled or disabled using OE (pin 4). Individual
clock outputs can be programmed to be sensitive to this OE pin.
I
2
C Programming
The MoBL
®
Clock M200 and M500 have a serial I
2
C interface
that programs the configuration memory array to synthesize
output frequencies by programmable output divider, spread
characteristics, and drive strength. I
2
C can also be used for
in-system control of these programmable features.
Input Reference Clocks
The input to the M200 and M500 are designed to use an external
reference clock with a frequency range of 1 MHz to 48 MHz at
the EXCLKIN pin. The voltage level for the input reference clock
used must follow VDD voltage used for the device as shown in
the DC and AC specifications.
Keep Alive Mode
By activating the device in the Keep Alive Mode, power down
mode is changed to power saving mode, which disables all PLLs
and outputs, but preserves the contents of the volatile registers.
Thus, any configuration changes made via the I
2
C interface are
preserved. By deactivating the Keep Alive Mode, I
2
C memory is
not preserved during power down, but power consumption is
reduced relative to the Keep Alive Mode.
Output Power Supply Options
There are three clock outputs CLK1, CLK2, and CLK3 driven by
three separate output power supplies: VDD_CLK1, VDD_CLK2,
and VDD_CLK3 respectively. Different voltage level for each of
these power supplies can be used and they can be any of 1.5V,
1.8V, 2.5V, 3.0V, or 3.3V giving user multiple choice of output
clock voltage levels.
Output Drive Strength
The DC drive strength of the individual clock output can be
programmed for different values.
Table 3
shows the typical rise
and fall times for different drive strength settings.
Table 3. Output Drive Strength
Output Drive Strength
Low
Mid Low
Mid High
High
Rise/Fall Time (ns)
(Typical Value)
6.8
3.4
2.0
1.0
Output Source Selection
These devices have three clock outputs, CLK1, CLK2 and CLK3.
There are three available clock sources for these outputs. These
clock sources are: PLL1, PLL2, or EXCLKIN. Output clock
source selection is done using three out of three crossbar switch.
Thus, any one of these three available clock sources can be
arbitrarily selected for the clock outputs. This gives user a flexi-
bility to have up to two independent clocks and a Reference clock
output.
Generic Configuration and Custom Frequency
The device is available with Factory Specific programmed
frequencies as shown in the Ordering Information page. This
factory specific programmed part can be used for the device
evaluation purposes. The MoBL
®
Clock can be custom
programmed to any desired frequencies and listed features. For
customer specific programming and I
2
C programmable memory
bitmap definitions, please contact local Cypress Field Appli-
cation Engineer (FAE) or sales representative.
Spread Spectrum Control
The PLL2 has spread spectrum capability for EMI reduction in
the system. The device uses a Cypress proprietary PLL and
Spread Spectrum Clock (SSC) technology to synthesize and
modulate the frequency of the PLL. The spread spectrum feature
can be turned on or off by I
2
C device programming. It can be
factory programmed to either center spread range from ±0.125%
Document #: 001-29139 Rev. *A
Page 4 of 14
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MoBL
®
Clock
M200/M500
I
2
C Serial Interface
To enhance the flexibility and function of the clock synthesizer, a
two-signal I
2
C serial interface is provided. This interface is used
to write (and optionally read) control registers that control various
device functions such as enabling individual clock output buffers.
The registers initialize to their default setting upon power up and
therefore, use of this interface is optional. Clock device registers
are normally changed upon system initialization. Any data written
via I
2
C is volatile and is not retained when the device is powered
down.
The I
2
C interface uses two signals, SDA and SCL, that operates
up to 400 kbits/s in Read or Write mode. The SDA and SCL
timing and data transfer sequence is shown in
Figure 3 on page
6.
The basic Write serial format is as follows:
Start Bit; 7-bit Device Address (DA); R/W Bit; Slave Clock
Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit
Data; ACK; 8-bit Data in MA+1 if desired; ACK; 8-bit Data in
MA+2; ACK; etc. until STOP Bit. The basic serial format is illus-
trated in
Figure 4 on page 6.
eight bits must contain the data word intended for storage. After
the receiving the data word, the slave responds with another
acknowledge bit (ack = 0/LOW), and the master must end the
write sequence with a STOP condition.
Writing Multiple Bytes
To write multiple bytes at a time, the master must not end the
write sequence with a STOP condition, but instead sends
multiple contiguous bytes of data to be stored. After each byte,
the slave responds with an acknowledge bit, the same as after
the first byte, and accepts data until the acknowledge bit is
responded to by the STOP condition. When receiving multiple
bytes, the MoBL Clock M2xx/M5xx internally increments the
register address.
Read Operations
Read operations are initiated the same way as Write operations
except that the R/W bit of the slave address is set to ‘1’ (HIGH).
There are three basic read operations: current address read,
random read, and sequential read.
Device Address
The device serial interface address is 69H. The device address
is combined with a read/write bit as the LSB and is sent after
each start bit.
Current Address Read
The MoBL Clock M2xx/M5xx have an onboard address counter
that retains ‘1’ more than the address of the last word accessed.
If the last word written or read was word ‘n’, then a current
address read operation returns the value stored in location ‘n+1’.
When the MoBL Clock M2xx/M5xx receives the slave address
with the R/W bit set to a ‘1’, it issues an acknowledge and
transmits the 8-bit word. The master device does not
acknowledge the transfer, but generates a STOP condition,
which causes the MoBL Clock M2xx/M5xx to stop transmission.
Data Valid
Data is valid when the clock is HIGH, and can only be transi-
tioned when the clock is LOW, as illustrated in
Figure 5 on page
6.
Data Frame
Every new data frame is indicated by a start and stop sequence,
as illustrated in
Figure 6 on page 7.
Start Sequence – SDA going LOW when SCL is HIGH indicates
a Start Frame. Every time a start signal is supplied, the next 8-bit
data must be the device address (seven bits) and a R/W bit,
followed by register address (eight bits) and register data (eight
bits).
Stop Sequence – SDA going HIGH when SCL is HIGH indicates
a Stop Frame. A Stop Frame frees the bus to write to another part
on the same bus or to write to another random register address.
Random Read
Through random read operations, the master may access any
memory location. To perform this type of read operation, first set
the word address. To do this, send the address to the MoBL
Clock M2xx/M5xx as part of a write operation. After the word
address is sent, the master generates a START condition
following the acknowledge. This terminates the write operation
before any data is stored in the address, but not before the
internal address pointer is set. Next, the master reissues the
control byte with the R/W byte set to ‘1’. The MoBL Clock
M2xx/M5xx then issues an acknowledge and transmits the 8-bit
word. The master device does not acknowledge the transfer, but
generates a STOP condition, which causes the MoBL Clock
M200/M500 to stop transmission.
Acknowledge Pulse
During Write Mode, the MoBL Clock M2xx/M5xx responds with
an Acknowledge pulse after every eight bits. This is done by
pulling the SDA line LOW during the N*9
th
clock cycle, as illus-
trated in
Figure 7 on page 7
(N = the number of bytes trans-
mitted). During Read Mode, the master generates the
acknowledge pulse after reading the data packet.
Sequential Read
Sequential read operations follow the same process as random
reads except that the master issues an acknowledge instead of
a STOP condition after transmission of the first 8-bit data word.
This action increments the internal address pointer, and subse-
quently outputs the next 8-bit data word. By continuing to issue
acknowledges instead of STOP conditions, the master serially
reads the entire contents of the slave device memory. When the
internal address pointer points to the FFH register, after the next
increment, the pointer points to the 00H register.
Write Operations
Writing Individual Bytes
A valid write operation must have a full 8-bit register address
after the device address word from the master, which is followed
by an acknowledge bit from the slave (ack = 0/LOW). The next
Document #: 001-29139 Rev. *A
Page 5 of 14
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