X68257
68XX Microcontroller Family Compatible
256K
X68257
E
2
Micro-Peripheral
DESCRIPTION
32,768 x 8 Bit
FEATURES
• Multiplexed Address/Data Bus
—Direct Interface to Popular 68HC11 Family
• High Performance CMOS
—Fast Access Time, 120ns
—Low Power
—60mA Active Maximum
—500
µ
A Standby Maximum
• Software Data Protection
• Toggle Bit Polling
—Early End of Write Detection
• Page Mode Write
—Allows up to 128 Bytes to be Written in
One Write Cycle
• High Reliability
—Endurance: 10,000 Write Cycle
—Data Retention: 100 Years
• 28-Lead PDIP Package
• 28-Lead SOIC Package
• 32-Lead PLCC Package
The X68257 is an 32K x 8 E
2
PROM fabricated with
advanced CMOS Textured Poly Floating Gate Technol-
ogy. The X68257 features a multiplexed address and
data bus allowing direct interface to a variety of popular
single-chip microcontrollers operating in expanded mul-
tiplexed mode without the need for additional interface
circuitry.
FUNCTIONAL DIAGRAM
CE, CE
R/W
E
SEL
A8–A14
CONTROL
LOGIC
X
D
E
C
O
D
E
SOFTWARE
DATA
PROTECT
AS
L
A
T
C
H
E
S
32K x 8
E2PROM
Y DECODE
I/O & ADDRESS LATCHES AND BUFFERS
A/D0–A/D7
6539 ILL F02.2
© Xicor, Inc. 1994, 1995, 1996 Patents Pending
6539-1.7 9/16/96 T0/C1/D2 SH
1
Characteristics subject to change without notice
X68257
PIN DESCRIPTIONS
Address/Data (A/D
0
–A/D
7
)
Multiplexed low-order addresses and data. The ad-
dresses flow into the device while AS is HIGH. After AS
transitions from a HIGH to LOW the addresses are
latched. Once the addresses are latched these pins
input data or output data depending on R/W,
SEL,
and
CE.
Addresses (A
8
–A
14
)
High order addresses flow into the device when AS = V
IH
and are latched when AS goes LOW.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When
CE
is HIGH, AS is LOW, and CE
is LOW, the X68257 is placed in the low power standby
mode.
Chip Enable (CE)
Chip Enable is active HIGH. When CE is used to select
the device, the CE must be tied HIGH.
Program Store Enable (SEL)
A12
PIN CONFIGURATION
PDIP
SOIC
A14
A12
AS
SEL
CE
NC
NC
NC
NC
NC
A/D0
A/D1
A/D2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
X68257
22
21
20
19
18
17
16
15
VCC
R/W
A13
A8
A9
A11
E
A10
CE
A/D7
A/D6
A/D5
A/D4
A/D3
6539 FHD F01.3
PLCC
VCC
R/W
A14
NC
AS
A13
When the X68257 is to be used in a 68XX-based
system,
SEL
is tied to V
SS
.
Read/Write (R/W)
When the X68257 is to be used in a 68XX-based
system, R/W is tied directly to the microcontroller’s R/W
output.
Address Strobe (AS)
Addresses flow through the latches to address decoders
when AS is HIGH and are latched when AS transitions
from a HIGH to LOW.
PIN NAMES
Symbol
AS
A/D
0
–A/D
7
A
8
–A
14
E
R/W
CE,
CE
SEL
V
SS
V
CC
NC
Description
Address Strobe
Address Inputs/Data I/O
Address Inputs
Enable Input
Read/Write Input
Chip Enable
Device Select—Connect to V
SS
Ground
Supply Voltage
No Connect
6539 PGM T01.2
SEL
CE
NC
NC
NC
NC
NC
NC
A/D0
4
5
6
7
8
9
10
11
12
3
2
1 32 31 30
29
28
27
26
25
24
23
22
A8
A9
A11
NC
E
A10
CE
A/D7
A/D6
X68257
13
21
14 15 16 17 18 19 20
A/D1
A/D2
VSS
NC
A/D3
A/D4
A/D5
6539 FHD F01A.5
2
X68257
PRINCIPLES OF OPERATION
The X68257 is a highly integrated peripheral device for
a wide variety of single-chip microcontrollers. The X68257
provides 32K-bytes of 5V E
2
PROM which can be used
either for program storage, data storage, or a combina-
tion of both, in systems based upon Von Neumann
(68XX) architectures. The X68257 incorporates the
interface circuitry normally needed to decode the control
signals and demultiplex the address/data bus to provide
a “seamless” interface.
The interface inputs on the X68257 are configured such
that it is possible to directly connect them to the proper
interface signals of the appropriate single-chip micro-
controller.
The X68257 features the industry standard 5V E
2
PROM
characteristics such as byte or page mode write and
Toggle Bit Polling.
Typical Application
U?
30
29
39
41
40
8
7
6
5
4
3
2
1
25
24
42
43
44
45
46
47
XTAL
EXTAL
RESET
IRQ
XIRQ
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
MODA
MODB
PD0
PD1
PD2
PD3
PD4
PD5
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
AS
R/W
MISO
MOSI
SCK
SS
E
PE0
PE1
PE2
PE3
VRH
VRL
68HC11
U?
31
32
33
34
35
36
37
38
16
15
14
13
12
11
10
9
26
28
27
17
18
19
20
22
21
11
12
12
15
16
17
18
19
25
24
21
23
2
26
1
5
3
27
22
A/D0
A/D1
A/D2
A/D3
A/D4
A/D5
A/D6
A/D7
A8
A9
A10
A11
A12
A13
A14
CE
AS
R/W
E
X68257
DEVICE OPERATION
Motorola 68XX operation requires the microcontroller
AS, E, and R/W outputs to be tied to the X68257 AS, E,
and R/W inputs respectively.
The falling edge of AS will latch the addresses for both
a read and write operation. The state of the R/W output
determines the operation to be performed, with the E
signal acting as a data strobe.
If R/W is HIGH and CE is HIGH (read operation) data will
be output on A/D
0
–A/D
7
after E transitions HIGH. If
R/W is LOW and CE is HIGH (write operation) data
present at A/D
0
–A/D
7
will be strobed into the X68257 on
the HIGH to LOW transition of E.
VCC
CE
SEL
20
4
6539 ILL F03.2
3
X68257
MODE SELECTION
CE
V
SS
LOW
HIGH
HIGH
E
X
X
HIGH
R/W
X
X
HIGH
LOW
Mode
Standby
Standby
Read
Write
I/O
High Z
High Z
D
OUT
D
IN
Power
Standby (CMOS)
Standby (TTL)
Active
Active
6539 PGM T02.2
PAGE WRITE OPERATION
Regardless of the microcontroller employed, the X68257
supports page mode write operations. This allows the
microcontroller to write from 1 to 128 bytes of data to the
X68257. Each individual write within a page write opera-
tion must conform to the byte write timing requirements.
The rising edge of E starts a timer delaying the internal
programming cycle 100µs. Therefore, each successive
write operation must begin within 100µs of the last byte
written. The following waveforms illustrate the sequence
and timing requirements.
Page Write Timing Sequence for E Controlled Operation
OPERATION
BYTE 0
BYTE 1
BYTE 2
LAST BYTE
READ (1)(2)
AFTER tWC READY FOR
NEXT WRITE OPERATION
CE
AS
A/D0–A/D7
AIN
DIN
AIN
DIN
AIN
DIN
AIN
DIN
AIN
DIN
AIN
AIN
A8–A14
An
An
An
An
An
ADDR
Next Address
E
R/W
tBLC
tWC
6539 FHD F07.1
Note:
(1) For each successive write within a page write cycle A
7
–A
14
must be the same.
4
X68257
Toggle Bit Polling
Because the typical write timing is less than the specified
5ms, Toggle Bit Polling has been provided to determine
the early end of write. During the internal programming
cycle I/O
6
will toggle from “1” to “0” and “0” to “1” on
Toggle Bit Polling E Control
subsequent attempts to read the device. When the
internal cycle is complete, the toggling will cease and the
device will be accessible for additional read or write
operations.
OPERATION
LAST BYTE
WRITTEN
I/O6=X
I/O6=X
I/O6=X
I/O6=X
X68257 READY FOR
NEXT OPERATION
CE
AS
A/D0–A/D7
AIN
DIN
AIN
DOUT
AIN
DOUT
AIN
DOUT
AIN
DOUT
AIN
A8–A14
An
An
An
An
An
ADDR
E
R/W
6539 FHD F08.2
5
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