DATASHEET
X5323, X5325 (Replaces X25323, X25325)
CPU Supervisor with 32kBit SPI EEPROM
These devices combine four popular functions, Power-on
Reset Control, Watchdog Timer, Supply Voltage Supervision,
and Block Lock Protect Serial EEPROM Memory in one
package. This combination lowers system cost, reduces
board space requirements, and increases reliability.
Applying power to the device activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and oscillator to stabilize
before the processor can execute code.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontroller
fails to restart a timer within a selectable time out interval,
the device activates the RESET/RESET signal. The user
selects the interval from three preset values. Once selected,
the interval does not change, even after cycling the power.
The device’s low V
CC
detection circuitry protects the user’s
system from low voltage conditions, resetting the system
when V
CC
falls below the minimum V
CC
trip point.
RESET/RESET is asserted until V
CC
returns to proper
operating level and stabilizes. Five industry standard V
TRIP
thresholds are available, however, Intersil’s unique circuits
allow the threshold to be reprogrammed to meet custom
requirements or to fine-tune the threshold for applications
requiring higher precision.
FN8131
Rev 3.00
December 9, 2015
Features
• Selectable watchdog timer
• Low V
CC
detection and reset assertion
- Five standard reset threshold voltages
- Re-program low V
CC
reset threshold voltage using
special programming sequence
- Reset signal valid to V
CC
= 1V
• Determine watchdog or low voltage reset with a volatile
flag bit
• Long battery life with low power consumption
- <50µA max standby current, watchdog on
- <1µA max standby current, watchdog off
- <400µA max active current during read
• 32kbits of EEPROM
• Built-in inadvertent write protection
- Power-up/power-down protection circuitry
- Protect 0, 1/4, 1/2 or all of EEPROM array with Block
Lock
™
protection
- In circuit programmable ROM mode
• 2MHz SPI interface modes (0,0 and 1,1)
• Minimize EEPROM programming time
- 32-byte page write mode
- Self-timed write cycle
- 5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V power supply
operation
• Available packages
- 14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP
• Pb-free (RoHS compliant)
Block Diagram
WATCHDOG TRANSITION
DETECTOR
WP
SI
SO
SCK
CS/WDI
DATA
REGISTER
COMMAND
DECODE AND
CONTROL
LOGIC
V
CC
THRESHOLD
RESET LOGIC
PROTECT LOGIC
RESET/RESET
STATUS
REGISTER
8kBITS
8kBITS
16kBITS
EEPROM ARRAY
RESET AND
WATCHDOG
TIMEBASE
X5323 = RESET
X5325 = RESET
WATCHDOG
TIMER RESET
V
CC
V
TRIP
+
-
POWER-ON AND
LOW VOLTAGE
RESET
GENERATION
FN8131 Rev 3.00
December 9, 2015
Page 1 of 19
X5323, X5325 (Replaces X25323, X25325)
Ordering Information
PART NUMBER
RESET (Active Low)
X5323PZ-4.5A (Note)
(No longer available, recommended
replacement: X5323S8Z-4.5A)
X5323PIZ-4.5A (Note)
(No longer available, recommended
replacement: X5323S8IZ-4.5A)
X5323S8Z-4.5A (Note)
X5323S8IZ-4.5A* (Note)
X5323V14-4.5A
X5323PZ (Note)
(No longer available, recommended
replacement: X5323S8Z)
X5323PIZ (Note)
(No longer available, recommended
replacement: X5323S8IZ)
X5323S8Z* (Note)
X5323S8IZ* (Note)
X5323PZ-2.7A (Note)
(No longer available, recommended
replacement: X5323S8Z-2.7A)
X5323PIZ-2.7A (Note)
(No longer available, recommended
replacement: X5323S8IZ-2.7A)
X5323S8Z-2.7A* (Note)
X5323S8IZ-2.7A* (Note)
X5323PZ-2.7 (Note)
(No longer available, recommended
replacement: X5323S8Z-2.7)
X5323PIZ-2.7 (Note)
(No longer available, recommended
replacement: X5323S8IZ-2.7)
X5323S8Z-2.7* (Note)
X5323S8IZ-2.7* (Note)
RESET (Active High)
X5325S8Z-4.5A (Note)
X5325S8IZ-4.5A (Note)
X5325S8Z* (Note)
X5325S8IZ* (Note)
X5325S8Z-2.7A (Note)
X5325S8IZ-2.7A (Note)
X5325S8Z-2.7* (Note)
X5325S8IZ-2.7* (Note)
X5325 ZAL
X5325 ZAM
X5325 Z
X5325 ZI
X5325 ZAN
X5325 ZAP
X5325 ZF
X5325 ZG
2.7 to 5.5
2.55 to 2.7
2.7 to 5.5
2.85 to 3.0
4.5 to 5.5
4.25 to 4.5
4.5 to 5.5
4.5 to 4.75
0 to +70
-40 to +85
0 to +70
-40 to +85
0 to +70
-40 to +85
0 to +70
-40 to +85
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
X5323P ZAL
4.5 to 5.5
4.5 to 4.75
0 to +70
8 Ld PDIP** (Pb-free)
PART MARKING
V
CC
RANGE
(V)
V
TRIP
RANGE TEMP RANGE
(V)
(°C)
PACKAGE
X5323P ZAM
-40 to +85
8 Ld PDIP** (Pb-free)
X5323 ZAL
X5323 ZAM
X5323 VAL
X5323P Z
4.5 to 5.5
4.25 to 4.5
0 to +70
-40 to +85
0 to +70
0 to +70
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
14 Ld TSSOP
8 Ld PDIP** (Pb-free)
X5323P ZI
-40 to +85
8 Ld PDIP** (Pb-free)
X5323 Z
X5323 ZI
X5323P ZAN
2.7 to 5.5
2.85 to 3.0
0 to +70
-40 to +85
0 to +70
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
8 Ld PDIP** (Pb-free)
X5323P ZAP
-40 to +85
8 Ld PDIP** (Pb-free)
X5323 ZAN
X5323 ZAP
X5323P ZF
2.7 to 5.5
2.55 to 2.7
0 to +70
-40 to +85
0 to +70
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
8 Ld PDIP** (Pb-free)
X5323P ZG
-40 to +85
8 Ld PDIP** (Pb-free)
X5323 ZF
X5323 ZG
0 to +70
-40 to +85
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
*Add “-T1” for tape and reel. Please refer to TB347 for details on reel specifications.
**Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
FN8131 Rev 3.00
December 9, 2015
Page 2 of 19
X5323, X5325 (Replaces X25323, X25325)
Pinouts
X5323, X5325
(8 LD SOIC, PDIP)
TOP VIEW
CS/WDI
SO
WP
V
SS
1
2
3
4
8
7
6
5
V
CC
RESET/RESET
SCK
SI
CS/WDI
SO
NC
NC
NC
WP
V
SS
X5323, X5325
(14 LD TSSOP)
TOP VIEW
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
RESET/RESET
NC
NC
NC
SCK
SI
Pin Descriptions
PIN NUMBER
(SOIC/PDIP)
1
PIN NUMBER
TSSOP
1
PIN NAME
CS/WDI
PIN FUNCTION
Chip Select Input.
CS HIGH, deselects the device and the SO output pin is at a high impedance
state. Unless a nonvolatile write cycle is underway, the device will be in the stand-by power mode.
CS LOW enables the device, placing it in the active power mode. Prior to the start of any operation
after power-up, a HIGH to LOW transition on CS is required.
Watchdog Input.
A HIGH to LOW transition on the WDI pin restarts the watchdog timer. The
absence of a HIGH to LOW transition within the watchdog time out period results in
RESET/RESET going active.
Serial Output.
SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The
falling edge of the serial clock (SCK) clocks the data out.
Serial Input.
SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this
pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1),
addresses and data MSB first.
Serial Clock.
The serial clock controls the serial bus timing for data input and output. The rising edge
of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK
changes the data output on the SO pin.
Write Protect.
The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting
of the watchdog timer control and the memory write protect bits.
Ground
Supply Voltage
Reset Output.
RESET/RESET is an active LOW/HIGH, open drain output which goes active
whenever V
CC
falls below the minimum V
CC
sense level. It will remain active until V
CC
rises above
the minimum V
CC
sense level for 200ms. RESET/RESET goes active if the watchdog timer is
enabled and CS remains either HIGH or LOW longer than the selectable watchdog time out
period. A falling edge of CS will reset the watchdog timer. RESET/RESET goes active on power-
up at about 1V and remains active for 200ms after the power supply stabilizes.
No internal connections
2
5
2
8
SO
SI
6
9
SCK
3
4
8
7
6
7
14
13
WP
V
SS
V
CC
RESET/
RESET
3 to 5,10 to 12
NC
FN8131 Rev 3.00
December 9, 2015
Page 3 of 19
X5323, X5325 (Replaces X25323, X25325)
Principles of Operation
Power-on Reset
Application of power to the X5323/X5325 activates a power-on
reset circuit. This circuit goes active at about 1V and pulls the
RESET/RESET pin active. This signal prevents the system
microprocessor from starting to operate with insufficient voltage
or prior to stabilization of the oscillator. As long as
RESET/RESET pin is active, the device will not respond to any
Read/Write instruction. When V
CC
exceeds the device V
TRIP
value for 200ms (nominal) the circuit releases RESET/RESET,
allowing the processor to begin executing code.
and pulse CS/WDI LOW then HIGH. Remove V
P
and the
sequence is complete.
CS
V
P
SCK
V
P
SI
FIGURE 1. SET V
TRIP
VOLTAGE
Low Voltage Monitoring
During operation, the X5323/X5325 monitors the V
CC
level and
asserts RESET/RESET if supply voltage falls below a preset
minimum V
TRIP
. The RESET/RESET signal prevents the
microprocessor from operating in a power fail or brown-out
condition. The RESET/RESET signal remains active until the
voltage drops below 1V. It also remains active until V
CC
returns
and exceeds V
TRIP
for 200ms.
Resetting the V
TRIP
Voltage
This procedure sets the V
TRIP
to a “native” voltage level. For
example, if the current V
TRIP
is 4.4V and the V
TRIP
is reset, the
new V
TRIP
is something less than 1.7V. This procedure must
be used to set the voltage to a lower value.
To reset the V
TRIP
voltage, apply a voltage between 2.7V and
5.5V to the VCC pin. Tie the CS/WDI pin, the WP pin, and the
SCK pin HIGH. RESET/RESET and SO pins are left
unconnected. Then apply the programming voltage V
P
to the
SI pin ONLY and pulse CS/WDI LOW then HIGH. Remove V
P
and the sequence is complete.
CS
V
CC
Watchdog Timer
The watchdog timer circuit monitors the microprocessor activity
by monitoring the WDI input. The microprocessor must toggle the
CS/WDI pin periodically to prevent a RESET/RESET signal.
The CS/WDI pin must be toggled from HIGH to LOW prior to
the expiration of the watchdog time out period. The state of two
nonvolatile control bits in the status register determine the
watchdog timer period. The microprocessor can change these
watchdog bits, or they may be “locked” by tying the WP pin
LOW and setting the WPEN bit HIGH.
SCK
V
P
SI
V
CC
Threshold Reset Procedure
The X5323/X5325 has a standard V
CC
threshold (V
TRIP
)
voltage. This value will not change over normal operating and
storage conditions. However, in applications where the
standard V
TRIP
is not exactly right, or for higher precision in the
V
TRIP
value, the X5323/X5325 threshold may be adjusted.
FIGURE 2. RESET V
TRIP
VOLTAGE
Setting the V
TRIP
Voltage
This procedure sets the V
TRIP
to a higher voltage value. For
example, if the current V
TRIP
is 4.4V and the new V
TRIP
is 4.6V,
this procedure directly makes the change. If the new setting is
lower than the current setting, then it is necessary to reset the
trip point before setting the new value.
To set the new V
TRIP
voltage, apply the desired V
TRIP
threshold to the VCC pin and tie the CS/WDI pin and the WP
pin HIGH. RESET/RESET and SO pins are left unconnected.
Then apply the programming voltage V
P
to both SCK and SI
FN8131 Rev 3.00
December 9, 2015
Page 4 of 19
X5323, X5325 (Replaces X25323, X25325)
V
TRIP
PROGRAMMING
EXECUTE
RESET V
TRIP
SEQUENCE
SET V
CC
= V
CC
APPLIED =
DESIRED V
TRIP
NEW V
CC
APPLIED =
OLD V
CC
APPLIED + ERROR
EXECUTE
SET V
TRIP
SEQUENCE
NEW V
CC
APPLIED =
OLD V
CC
APPLIED - ERROR
APPLY 5V TO V
CC
EXECUTE
RESET V
TRIP
SEQUENCE
DECREMENT V
CC
(V
CC
= V
CC
- 10mV)
NO
RESET PIN
GOES ACTIVE?
YES
ERROR
EMAX
MEASURED V
TRIP
-
DESIRED V
TRIP
ERROR < EMAX
ERROR
EMAX
EMAX = MAXIMUM DESIRED ERROR
DONE
FIGURE 3. V
TRIP
PROGRAMMING SEQUENCE FLOW CHART
V
P
4.7k
V
TRIP
ADJ.
+
PROGRAM
NC
1
2
3
4
X5323,
X5325
8
7
6
5
NC
NC
4.7k
RESET
10k
10k
RESET V
TRIP
TEST V
TRIP
SET V
TRIP
FIGURE 4. SAMPLE V
TRIP
RESET CIRCUIT
FN8131 Rev 3.00
December 9, 2015
Page 5 of 19
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