K4S280432A-TC80 datasheet, PDF

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K4S280432A-TC80: DescriptionSynchronous DRAM, 32MX4, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54; Categorystorage storage; File Size110KB，10 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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K4S280432A-TC80 Overview

Synchronous DRAM, 32MX4, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54

K4S280432A-TC80 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	SAMSUNG
Parts packaging code	TSOP2
package instruction	TSOP2, TSOP54,.46,32
Contacts	54
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	6 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	125 MHz
I/O type	COMMON
interleaved burst length	1,2,4,8
JESD-30 code	R-PDSO-G54
JESD-609 code	e0
length	22.22 mm
memory density	134217728 bit
Memory IC Type	SYNCHRONOUS DRAM
memory width	4
Number of functions	1
Number of ports	1
Number of terminals	54
word count	33554432 words
character code	32000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	32MX4
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Encapsulate equivalent code	TSOP54,.46,32
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3 V
Certification status	Not Qualified
refresh cycle	4096
Maximum seat height	1.2 mm
self refresh	YES
Continuous burst length	1,2,4,8,FP
Maximum standby current	0.001 A
Maximum slew rate	0.22 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	10.16 mm

K4S280432A-TC80 Preview

K4S280432A

CMOS SDRAM

128Mbit SDRAM

8M x 4Bit x 4 Banks

Synchronous DRAM

LVTTL

Revision 0.0

Aug. 1999

* Samsung Electronics reserves the right to change products or specification without notice.

Rev. 0.0 Aug. 1999

K4S280432A

8M x 4Bit x 4 Banks Synchronous DRAM

FEATURES

•

JEDEC standard 3.3V power supply

LVTTL compatible with multiplexed address

Four banks operation

MRS cycle with address key programs

-. CAS latency (2 & 3)

-. Burst length (1, 2, 4, 8 Page )

-. Burst type (Sequential & Interleave)

All inputs are sampled at the positive going edge of the system

clock.

Burst read single-bit write operation

DQM for masking

Auto & self refresh

64ms refresh period (4K Cycle)

CMOS SDRAM

GENERAL DESCRIPTION

The

K4S280432A

is 134,217,728 bits synchronous high data

rate Dynamic RAM organized as 4 x 8,388,608 words by 4 bits,

fabricated with SAMSUNG′s high performance CMOS technol-

ogy. Synchronous design allows precise cycle control with the

use of system clock I/O transactions are possible on every clock

cycle. Range of operating frequencies, programmable burst

length and programmable latencies allow the same device to be

useful for a variety of high bandwidth, high performance mem-

ory system applications.

•

ORDERING INFORMATION

Part No.

K4S280432A-TC/L75

K4S280432A-TC/L80

K4S280432A-TC/L1H

K4S280432A-TC/L1L

K4S280432A-TC/L10

Max Freq.

133MHz(CL=3)

125MHz(CL=3)

100MHz(CL=2)

100MHz(CL=3)

66MHz(CL=2 &3)

LVTTL

TSOP(II)

Interface Package

FUNCTIONAL BLOCK DIAGRAM

I/O Control

LWE

LDQM

Data Input Register

Bank Select

8M x 4

Sense AMP

8M x 4

Refresh Counter

Output Buffer

Row Decoder

Row Buffer

DQi

Address Register

CLK

ADD

Column Decoder

Col. Buffer

Latency & Burst Length

LRAS

LCBR

LCKE

LRAS

LCBR

LWE

LCAS

Timing Register

Programming Register

LWCBR

LDQM

CLK

CKE

RAS

CAS

DQM

* Samsung Electronics reserves the right to change products or specification without notice.

Rev. 0.0 Aug. 1999

K4S280432A

PIN CONFIGURATION

(Top view)

N.C

DDQ

N.C

DQ0

SSQ

N.C

DDQ

N.C

DQ1

SSQ

N.C

CAS

RAS

BA0

BA1

A10/AP

N.C

SSQ

N.C

DQ3

DDQ

N.C

SSQ

N.C

DQ2

DDQ

N.C

N.C/RFU

DQM

CLK

CKE

N.C

A11

CMOS SDRAM

54Pin TSOP (II)

(400mil x 875mil)

(0.8 mm Pin pitch)

PIN FUNCTION DESCRIPTION

CLK

Name

System clock

Chip select

Input Function

Active on the positive going edge to sample all inputs.

Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQM

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

Row/column addresses are multiplexed on the same pins.

Row address : RA

~ RA

, Column address : CA

~ CA

, CA

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

Makes data output Hi-Z, t

SHZ

after the clock and masks the output.

Blocks data input when DQM active.

Data inputs/outputs are multiplexed on the same pins.

Power and ground for the input buffers and the core logic.

Isolated power supply and ground for the output buffers to provide improved noise

immunity.

This pin is recommended to be left No Connection on the device.

CKE

Clock enable

~ A

~ BA

RAS

CAS

DQM

DDQ

SSQ

N.C/RFU

Address

Bank select address

Row address strobe

Column address strobe

Write enable

Data input/output mask

Data input/output

Power supply/ground

Data output power/ground

No connection

/reserved for future use

Rev. 0.0 Aug. 1999

K4S280432A

ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to Vss

Voltage on V

supply relative to Vss

Storage temperature

Power dissipation

Short circuit current

Symbol

, V

OUT

, V

DDQ

STG

Value

-1.0 ~ 4.6

-55 ~ +150

CMOS SDRAM

Unit

°C

Note :

Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS

Recommended operating conditions (voltage referenced to V

= 0V, T

= 0 to 70°C)

Parameter

Supply voltage

Input logic high voltage

Input logic low voltage

Output logic high voltage

Output logic low voltage

Input leakage current

Symbol

, V

DDQ

Min

3.0

2.0

-0.3

2.4

-10

Typ

3.3

3.0

Max

3.6

+0.3

0.8

0.4

Unit

= -2mA

= 2mA

Note

Notes :

1. V

(max) = 5.6V AC.The overshoot voltage duration is

≤

3ns.

2. V

(min) = -2.0V AC. The undershoot voltage duration is

≤

3ns.

3. Any input 0V

≤

DDQ

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

CAPACITANCE

Clock

= 3.3V, T

= 23°C, f = 1MHz, V

REF

=1.4V

200 mV)

Symbol

CLK

ADD

OUT

Min

2.5

4.0

Max

4.0

5.0

6.5

Unit

Note

RAS, CAS, WE, CS, CKE, DQM

Address

~ DQ

Notes :

1. -75 only specify a maximum value of 3.5pF

2. -75 only specify a maximum value of 3.8pF

3. -75 only specify a maximum value of 6.0pF

Rev. 0.0 Aug. 1999

K4S280432A

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, T

= 0 to 70°C)

Parameter

Symbol

Test Condition

-75

Operating current

(One bank active)

Precharge standby current in

power-down mode

CC1

CC2

Burst length = 1

≥

(min)

= 0 mA

CKE

≤

(max), t

= 10ns

CKE

≥

(min), CS

≥

(min), t

= 10ns

Input signals are changed one time during 20ns

120

-80

120

CMOS SDRAM

Version

-1H

110

-1L

-10

Unit

Note

110 110

CC2

PS CKE & CLK

≤

(max), t

∞

CC2

Precharge standby current in

non power-down mode

CKE

≥

(min), CLK

≤

(max), t

∞

CC2

Input signals are stable

CC3

CKE

≤

(max), t

= 10ns

CKE

≥

(min), CS

≥

(min), t

= 10ns

Input signals are changed one time during 20ns

CKE

≥

(min), CLK

≤

(max), t

∞

Input signals are stable

= 0 mA

Page burst

4Banks Activated

CCD

= 2CLKs

≥

(min)

CKE

≤

0.2V

Active standby current in

power-down mode

Active standby current in

non power-down mode

(One bank active)

CC3

PS CKE & CLK

≤

(max), t

∞

CC3

Operating current

(Burst mode)

Refresh current

Self refresh current

CC4

140

135

115

115 115

CC5

CC6

220

210

1.5

800

210 210

Notes :

1. Measured with outputs open.

2. Refresh period is 64ms.

3. K4S280432A-TC**

4. K4S280432A-TL**

5. Unless otherwise noted, input swing IeveI is CMOS(V

DDQ

SSQ)

Rev. 0.0 Aug. 1999

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