Preliminary
K4S561632B-TI(P)
CMOS SDRAM
256Mbit SDRAM
4M x 16bit x 4 Banks
Synchronous DRAM
LVTTL
Revision 0.0
January 2001
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.0 Jan. 2001
Preliminary
K4S561632B-TI(P)
Revision History
Revision 0.0 (January 20, 2001)
• First generation of 256Mb Industrial Temperature Part.
CMOS SDRAM
Rev. 0.0 Jan. 2001
Preliminary
K4S561632B-TI(P)
4M x 16Bit x 4 Banks Synchronous DRAM
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (8K Cycle)
•
Industrial Temperature Operation (- 40 to 85
°C)
CMOS SDRAM
GENERAL DESCRIPTION
The K4S561632B is 268,435,456 bits synchronous high data rate
Dynamic RAM organized as 4 x 4,196,304 words by 16 bits, fabri-
cated with SAMSUNG's high performance CMOS technology. Syn-
chronous design allows precise cycle control with the use of
system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and
programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system appli-
cations.
ORDERING INFORMATION
Part No.
K4S561632B-TI/P75
K4S561632B-TI/P1H
K4S561632B-TI/P1L
Max Freq.
133MHz(CL=3)
100MHz(CL=2)
100MHz(CL=3)
LVTTL
Interface
Package
54pin
TSOP(II)
FUNCTIONAL BLOCK DIAGRAM
I/O Control
LWE
Data Input Register
LDQM
Bank Select
4M x 16
4M x 16
4M x 16
4M x 16
Refresh Counter
Output Buffer
Row Decoder
Sense AMP
Row Buffer
DQi
Address Register
CLK
ADD
Column Decoder
Col. Buffer
LRAS
LCBR
Latency & Burst Length
LCKE
LRAS
LCBR
LWE
LCAS
Programming Register
LWCBR
LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.0 Jan. 2001
Preliminary
K4S561632B-TI(P)
PIN CONFIGURATION
(Top view)
V
DD
DQ0
V
DDQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
DDQ
DQ5
DQ6
V
SSQ
DQ7
V
DD
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ15
V
SSQ
DQ14
DQ13
V
DDQ
DQ12
DQ11
V
SSQ
DQ10
DQ9
V
DDQ
DQ8
V
SS
N.C/RFU
UDQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
CMOS SDRAM
54Pin TSOP (II)
(400mil x 875mil)
(0.8 mm Pin pitch)
PIN FUNCTION DESCRIPTION
Pin
CLK
CS
Name
System cock
Chip select
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column addresses are multiplexed on the same pins.
Row address : RA
0
~ RA
12
, Column address : CA
0
~ CA
8
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No Connection on the device.
CKE
Clock enable
A
0
~ A
12
BA
0
~ BA
1
RAS
CAS
WE
L(U)DQM
DQ
0
~
15
V
D D
/V
SS
V
DDQ
/V
SSQ
N.C/RFU
Address
Bank select address
Row address strobe
Column address strobe
Write enable
Data input/output mask
Data input/output
Power supply/ground
Data output power/ground
No connection
/reserved for future use
Rev. 0.0 Jan. 2001
Preliminary
K4S561632B-TI(P)
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on V
DD
supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Symbol
V
I N
, V
OUT
V
DD
, V
DDQ
T
S T G
P
D
I
OS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
50
CMOS SDRAM
Unit
V
V
°C
W
mA
Note :
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Parameter
Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= -40 to 85
°C)
Symbol
V
DD
, V
DDQ
V
IH
V
IL
V
O H
V
OL
I
LI
Min
3.0
2.0
-0.3
2.4
-
-10
Typ
3.3
3.0
0
-
-
-
Max
3.6
V
D D
+0.3
0.8
-
0.4
10
Unit
V
V
V
V
V
uA
1
2
I
O H
= -2mA
I
OL
= 2mA
3
Note
Notes :
1. V
IH
(max) = 5.6V AC. The overshoot voltage duration is
≤
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
≤
3ns.
3. Any input 0V
≤
V
IN
≤
V
DDQ
.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
Clock
(V
DD
= 3.3V, T
A
= 23°C, f = 1MHz, V
REF
=1.4V
±
200 mV)
Pin
Symbol
C
CLK
C
IN
C
ADD
C
OUT
Min
2.5
2.5
2.5
4.0
Max
4.0
5.0
5.0
6.5
Unit
pF
pF
pF
pF
Note
1
2
2
3
RAS, CAS, WE, CS, CKE, DQM
Address
D Q
0
~ DQ
15
Notes :
1. -75 only specify a maximum value of 3.5pF
2. -75 only specify a maximum value of 3.8pF
3. -75 only specify a maximum value of 6.0pF
Rev. 0.0 Jan. 2001
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